fdivision.hier_info

verilog hdl经典例程

|fdivision
RESET => j~15.OUTPUTSELECT
RESET => j~14.OUTPUTSELECT
RESET => j~13.OUTPUTSELECT
RESET => j~12.OUTPUTSELECT
RESET => j~11.OUTPUTSELECT
RESET => j~10.OUTPUTSELECT
RESET => j~9.OUTPUTSELECT
RESET => j~8.OUTPUTSELECT
RESET => F500K~1.OUTPUTSELECT
F10M => F500K~reg0.CLK
F10M => j[7].CLK
F10M => j[6].CLK
F10M => j[5].CLK
F10M => j[4].CLK
F10M => j[3].CLK
F10M => j[2].CLK
F10M => j[1].CLK
F10M => j[0].CLK
F500K <= F500K~reg0.DB_MAX_OUTPUT_PORT_TYPE