fdivision.tan.rpt

verilog hdl经典例程

; th                                                                      ;
+---------------+-------------+-----------+-------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To         ; To Clock ;
+---------------+-------------+-----------+-------+------------+----------+
; N/A           ; None        ; -2.682 ns ; RESET ; F500K~reg0 ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[4]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[3]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[5]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[2]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[0]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[7]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[6]       ; F10M     ;
; N/A           ; None        ; -3.136 ns ; RESET ; j[1]       ; F10M     ;
+---------------+-------------+-----------+-------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Sat May 16 11:32:44 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fdivision -c fdivision --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "F10M" is an undefined clock
Info: Clock "F10M" has Internal fmax of 495.54 MHz between source register "j[0]" and destination register "j[4]" (period= 2.018 ns)
    Info: + Longest register to register delay is 1.834 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 3; REG Node = 'j[0]'
        Info: 2: + IC(0.355 ns) + CELL(0.366 ns) = 0.721 ns; Loc. = LCCOMB_X15_Y15_N20; Fanout = 1; COMB Node = 'Equal0~103'
        Info: 3: + IC(0.195 ns) + CELL(0.053 ns) = 0.969 ns; Loc. = LCCOMB_X15_Y15_N16; Fanout = 2; COMB Node = 'Equal0~104'
        Info: 4: + IC(0.202 ns) + CELL(0.053 ns) = 1.224 ns; Loc. = LCCOMB_X15_Y15_N22; Fanout = 8; COMB Node = 'j[1]~49'
        Info: 5: + IC(0.213 ns) + CELL(0.397 ns) = 1.834 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j[4]'
        Info: Total cell delay = 0.869 ns ( 47.38 % )
        Info: Total interconnect delay = 0.965 ns ( 52.62 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "F10M" to destination register is 2.461 ns
            Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'
            Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'
            Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j[4]'
            Info: Total cell delay = 1.472 ns ( 59.81 % )
            Info: Total interconnect delay = 0.989 ns ( 40.19 % )
        Info: - Longest clock path from clock "F10M" to source register is 2.461 ns
            Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'
            Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'
            Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 3; REG Node = 'j[0]'
            Info: Total cell delay = 1.472 ns ( 59.81 % )
            Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "j[4]" (data pin = "RESET", clock pin = "F10M") is 3.375 ns
    Info: + Longest pin to register delay is 5.746 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 2; PIN Node = 'RESET'
        Info: 2: + IC(4.101 ns) + CELL(0.228 ns) = 5.136 ns; Loc. = LCCOMB_X15_Y15_N22; Fanout = 8; COMB Node = 'j[1]~49'
        Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.746 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j[4]'
        Info: Total cell delay = 1.432 ns ( 24.92 % )
        Info: Total interconnect delay = 4.314 ns ( 75.08 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "F10M" to destination register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N9; Fanout = 3; REG Node = 'j[4]'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
Info: tco from clock "F10M" to destination pin "F500K" through register "F500K~reg0" is 5.980 ns
    Info: + Longest clock path from clock "F10M" to source register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.425 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'
        Info: 2: + IC(1.463 ns) + CELL(1.962 ns) = 3.425 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'F500K'
        Info: Total cell delay = 1.962 ns ( 57.28 % )
        Info: Total interconnect delay = 1.463 ns ( 42.72 % )
Info: th for register "F500K~reg0" (data pin = "RESET", clock pin = "F10M") is -2.682 ns
    Info: + Longest clock path from clock "F10M" to destination register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'F10M'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'F10M~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.292 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 2; PIN Node = 'RESET'
        Info: 2: + IC(4.102 ns) + CELL(0.228 ns) = 5.137 ns; Loc. = LCCOMB_X15_Y15_N18; Fanout = 1; COMB Node = 'F500K~84'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.292 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 2; REG Node = 'F500K~reg0'
        Info: Total cell delay = 1.190 ns ( 22.49 % )
        Info: Total interconnect delay = 4.102 ns ( 77.51 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 130 megabytes
    Info: Processing ended: Sat May 16 11:32:45 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01