seqdet.tan.rpt

verilog hdl经典例程

+-------+--------------+------------+---------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From          ; To       ; From Clock ;
+-------+--------------+------------+---------------+----------+------------+
; N/A   ; None         ; 6.500 ns   ; state[0]~reg0 ; z        ; clk        ;
; N/A   ; None         ; 6.345 ns   ; state[2]~reg0 ; z        ; clk        ;
; N/A   ; None         ; 6.214 ns   ; state[2]~reg0 ; state[2] ; clk        ;
; N/A   ; None         ; 6.197 ns   ; state[1]~reg0 ; z        ; clk        ;
; N/A   ; None         ; 6.076 ns   ; state[0]~reg0 ; state[0] ; clk        ;
; N/A   ; None         ; 6.073 ns   ; state[1]~reg0 ; state[1] ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 8.469 ns        ; x    ; z  ;
+-------+-------------------+-----------------+------+----+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+------+---------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To            ; To Clock ;
+---------------+-------------+-----------+------+---------------+----------+
; N/A           ; None        ; -2.797 ns ; x    ; state[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.798 ns ; x    ; state[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.798 ns ; x    ; state[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.148 ns ; rst  ; state[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.148 ns ; rst  ; state[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.148 ns ; rst  ; state[1]~reg0 ; clk      ;
+---------------+-------------+-----------+------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Mon May 18 10:32:17 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seqdet -c seqdet --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "state[0]~reg0" and destination register "state[1]~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.730 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state[0]~reg0'
            Info: 2: + IC(0.347 ns) + CELL(0.228 ns) = 0.575 ns; Loc. = LCCOMB_X18_Y12_N18; Fanout = 1; COMB Node = 'state~362'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.730 ns; Loc. = LCFF_X18_Y12_N19; Fanout = 5; REG Node = 'state[1]~reg0'
            Info: Total cell delay = 0.383 ns ( 52.47 % )
            Info: Total interconnect delay = 0.347 ns ( 47.53 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.468 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N19; Fanout = 5; REG Node = 'state[1]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.64 % )
                Info: Total interconnect delay = 0.996 ns ( 40.36 % )
            Info: - Longest clock path from clock "clk" to source register is 2.468 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state[0]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.64 % )
                Info: Total interconnect delay = 0.996 ns ( 40.36 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "state[0]~reg0" (data pin = "rst", clock pin = "clk") is 3.387 ns
    Info: + Longest pin to register delay is 5.765 ns
        Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_T19; Fanout = 3; PIN Node = 'rst'
        Info: 2: + IC(4.434 ns) + CELL(0.366 ns) = 5.610 ns; Loc. = LCCOMB_X18_Y12_N16; Fanout = 1; COMB Node = 'state~361'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.765 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state[0]~reg0'
        Info: Total cell delay = 1.331 ns ( 23.09 % )
        Info: Total interconnect delay = 4.434 ns ( 76.91 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.468 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state[0]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.64 % )
        Info: Total interconnect delay = 0.996 ns ( 40.36 % )
Info: tco from clock "clk" to destination pin "z" through register "state[0]~reg0" is 6.500 ns
    Info: + Longest clock path from clock "clk" to source register is 2.468 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state[0]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.64 % )
        Info: Total interconnect delay = 0.996 ns ( 40.36 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.938 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state[0]~reg0'
        Info: 2: + IC(0.503 ns) + CELL(0.225 ns) = 0.728 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 1; COMB Node = 'z~0'
        Info: 3: + IC(1.212 ns) + CELL(1.998 ns) = 3.938 ns; Loc. = PIN_Y12; Fanout = 0; PIN Node = 'z'
        Info: Total cell delay = 2.223 ns ( 56.45 % )
        Info: Total interconnect delay = 1.715 ns ( 43.55 % )
Info: Longest tpd from source pin "x" to destination pin "z" is 8.469 ns
    Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AA12; Fanout = 4; PIN Node = 'x'
    Info: 2: + IC(4.104 ns) + CELL(0.346 ns) = 5.259 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 1; COMB Node = 'z~0'
    Info: 3: + IC(1.212 ns) + CELL(1.998 ns) = 8.469 ns; Loc. = PIN_Y12; Fanout = 0; PIN Node = 'z'
    Info: Total cell delay = 3.153 ns ( 37.23 % )
    Info: Total interconnect delay = 5.316 ns ( 62.77 % )
Info: th for register "state[2]~reg0" (data pin = "x", clock pin = "clk") is -2.797 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.468 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N21; Fanout = 5; REG Node = 'state[2]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.64 % )
        Info: Total interconnect delay = 0.996 ns ( 40.36 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.414 ns
        Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AA12; Fanout = 4; PIN Node = 'x'
        Info: 2: + IC(4.104 ns) + CELL(0.346 ns) = 5.259 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 1; COMB Node = 'state~363'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.414 ns; Loc. = LCFF_X18_Y12_N21; Fanout = 5; REG Node = 'state[2]~reg0'
        Info: Total cell delay = 1.310 ns ( 24.20 % )
        Info: Total interconnect delay = 4.104 ns ( 75.80 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 131 megabytes
    Info: Processing ended: Mon May 18 10:32:18 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01