seqdet.fit.summary

来自「verilog hdl经典例程」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Mon May 18 10:32:11 2009
Quartus II Version : 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
Revision Name : seqdet
Top-level Entity Name : seqdet
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 4 / 12,480 ( < 1 % )
    Dedicated logic registers : 3 / 12,480 ( < 1 % )
Total registers : 3
Total pins : 7 / 343 ( 2 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )