seqdet.tan.qmsg

verilog hdl经典例程

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register state\[0\]~reg0 state\[1\]~reg0 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"state\[0\]~reg0\" and destination register \"state\[1\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.730 ns + Longest register register " "Info: + Longest register to register delay is 0.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\]~reg0 1 REG LCFF_X18_Y12_N17 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[0]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.347 ns) + CELL(0.228 ns) 0.575 ns state~362 2 COMB LCCOMB_X18_Y12_N18 1 " "Info: 2: + IC(0.347 ns) + CELL(0.228 ns) = 0.575 ns; Loc. = LCCOMB_X18_Y12_N18; Fanout = 1; COMB Node = 'state~362'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.575 ns" { state[0]~reg0 state~362 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.730 ns state\[1\]~reg0 3 REG LCFF_X18_Y12_N19 5 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.730 ns; Loc. = LCFF_X18_Y12_N19; Fanout = 5; REG Node = 'state\[1\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { state~362 state[1]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns ( 52.47 % ) " "Info: Total cell delay = 0.383 ns ( 52.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.347 ns ( 47.53 % ) " "Info: Total interconnect delay = 0.347 ns ( 47.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { state[0]~reg0 state~362 state[1]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.730 ns" { state[0]~reg0 {} state~362 {} state[1]~reg0 {} } { 0.000ns 0.347ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.468 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns state\[1\]~reg0 3 REG LCFF_X18_Y12_N19 5 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N19; Fanout = 5; REG Node = 'state\[1\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk~clkctrl state[1]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[1]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[1]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.468 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns state\[0\]~reg0 3 REG LCFF_X18_Y12_N17 5 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[1]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[1]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.730 ns" { state[0]~reg0 state~362 state[1]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.730 ns" { state[0]~reg0 {} state~362 {} state[1]~reg0 {} } { 0.000ns 0.347ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[1]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[1]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[1]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { state[1]~reg0 {} } {  } {  } "" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "state\[0\]~reg0 rst clk 3.387 ns register " "Info: tsu for register \"state\[0\]~reg0\" (data pin = \"rst\", clock pin = \"clk\") is 3.387 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.765 ns + Longest pin register " "Info: + Longest pin to register delay is 5.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns rst 1 PIN PIN_T19 3 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_T19; Fanout = 3; PIN Node = 'rst'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.434 ns) + CELL(0.366 ns) 5.610 ns state~361 2 COMB LCCOMB_X18_Y12_N16 1 " "Info: 2: + IC(4.434 ns) + CELL(0.366 ns) = 5.610 ns; Loc. = LCCOMB_X18_Y12_N16; Fanout = 1; COMB Node = 'state~361'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { rst state~361 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.765 ns state\[0\]~reg0 3 REG LCFF_X18_Y12_N17 5 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.765 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { state~361 state[0]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns ( 23.09 % ) " "Info: Total cell delay = 1.331 ns ( 23.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.434 ns ( 76.91 % ) " "Info: Total interconnect delay = 4.434 ns ( 76.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.765 ns" { rst state~361 state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.765 ns" { rst {} rst~combout {} state~361 {} state[0]~reg0 {} } { 0.000ns 0.000ns 4.434ns 0.000ns } { 0.000ns 0.810ns 0.366ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.468 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns state\[0\]~reg0 3 REG LCFF_X18_Y12_N17 5 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.765 ns" { rst state~361 state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.765 ns" { rst {} rst~combout {} state~361 {} state[0]~reg0 {} } { 0.000ns 0.000ns 4.434ns 0.000ns } { 0.000ns 0.810ns 0.366ns 0.155ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk z state\[0\]~reg0 6.500 ns register " "Info: tco from clock \"clk\" to destination pin \"z\" through register \"state\[0\]~reg0\" is 6.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.468 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 3 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 3; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns state\[0\]~reg0 3 REG LCFF_X18_Y12_N17 5 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.938 ns + Longest register pin " "Info: + Longest register to pin delay is 3.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\]~reg0 1 REG LCFF_X18_Y12_N17 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 5; REG Node = 'state\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[0]~reg0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.503 ns) + CELL(0.225 ns) 0.728 ns z~0 2 COMB LCCOMB_X18_Y12_N22 1 " "Info: 2: + IC(0.503 ns) + CELL(0.225 ns) = 0.728 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 1; COMB Node = 'z~0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.728 ns" { state[0]~reg0 z~0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(1.998 ns) 3.938 ns z 3 PIN PIN_Y12 0 " "Info: 3: + IC(1.212 ns) + CELL(1.998 ns) = 3.938 ns; Loc. = PIN_Y12; Fanout = 0; PIN Node = 'z'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.210 ns" { z~0 z } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.223 ns ( 56.45 % ) " "Info: Total cell delay = 2.223 ns ( 56.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.715 ns ( 43.55 % ) " "Info: Total interconnect delay = 1.715 ns ( 43.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.938 ns" { state[0]~reg0 z~0 z } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.938 ns" { state[0]~reg0 {} z~0 {} z {} } { 0.000ns 0.503ns 1.212ns } { 0.000ns 0.225ns 1.998ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl state[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} state[0]~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.938 ns" { state[0]~reg0 z~0 z } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.938 ns" { state[0]~reg0 {} z~0 {} z {} } { 0.000ns 0.503ns 1.212ns } { 0.000ns 0.225ns 1.998ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "x z 8.469 ns Longest " "Info: Longest tpd from source pin \"x\" to destination pin \"z\" is 8.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.809 ns) 0.809 ns x 1 PIN PIN_AA12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_AA12; Fanout = 4; PIN Node = 'x'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.104 ns) + CELL(0.346 ns) 5.259 ns z~0 2 COMB LCCOMB_X18_Y12_N22 1 " "Info: 2: + IC(4.104 ns) + CELL(0.346 ns) = 5.259 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 1; COMB Node = 'z~0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.450 ns" { x z~0 } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(1.998 ns) 8.469 ns z 3 PIN PIN_Y12 0 " "Info: 3: + IC(1.212 ns) + CELL(1.998 ns) = 8.469 ns; Loc. = PIN_Y12; Fanout = 0; PIN Node = 'z'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.210 ns" { z~0 z } "NODE_NAME" } } { "seqdet.v" "" { Text "E:/lab/seqdet.v/seqdet.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.153 ns ( 37.23 % ) " "Info: Total cell delay = 3.153 ns ( 37.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.316 ns ( 62.77 % ) " "Info: Total interconnect delay = 5.316 ns ( 62.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.469 ns" { x z~0 z } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "8.469 ns" { x {} x~combout {} z~0 {} z {} } { 0.000ns 0.000ns 4.104ns 1.212ns } { 0.000ns 0.809ns 0.346ns 1.998ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}