seqdet.hier_info

verilog hdl经典例程

|seqdet
x => Mux2.IN7
x => Mux0.IN7
x => state~8.OUTPUTSELECT
x => state~7.OUTPUTSELECT
x => state~6.OUTPUTSELECT
x => state~2.OUTPUTSELECT
x => state~1.OUTPUTSELECT
x => state~0.OUTPUTSELECT
x => Mux2.IN2
x => Mux2.IN3
x => Mux1.IN2
x => Mux1.IN3
x => Mux1.IN4
x => state~3.OUTPUTSELECT
x => state~4.OUTPUTSELECT
x => state~5.OUTPUTSELECT
x => Mux0.IN3
x => z~0.IN0
z <= z~0.DB_MAX_OUTPUT_PORT_TYPE
clk => state[2]~reg0.CLK
clk => state[1]~reg0.CLK
clk => state[0]~reg0.CLK
rst => state~11.OUTPUTSELECT
rst => state~10.OUTPUTSELECT
rst => state~9.OUTPUTSELECT
state[0] <= state[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state[1] <= state[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state[2] <= state[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE