seqdet.hif

verilog hdl经典例程

Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
7
2834
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
seqdet
# storage
db|seqdet.(0).cnf
db|seqdet.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
seqdet.v
93153d74f3fea7f873a047527c20202b
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
IDLE
00000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
DEF
A
00000000000000000000000000000001
PARAMETER_UNSIGNED_BIN
DEF
B
00000000000000000000000000000010
PARAMETER_UNSIGNED_BIN
DEF
C
00000000000000000000000000000011
PARAMETER_UNSIGNED_BIN
DEF
D
00000000000000000000000000000100
PARAMETER_UNSIGNED_BIN
DEF
E
00000000000000000000000000000101
PARAMETER_UNSIGNED_BIN
DEF
F
00000000000000000000000000000110
PARAMETER_UNSIGNED_BIN
DEF
G
00000000000000000000000000000111
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
|
}
# macro_sequence

# end
# complete