seqdet.map.summary

verilog hdl经典例程

Analysis & Synthesis Status : Successful - Mon May 18 10:32:06 2009
Quartus II Version : 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
Revision Name : seqdet
Top-level Entity Name : seqdet
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 4
    Dedicated logic registers : 3
Total registers : 3
Total pins : 7
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0