seqdet.map.rpt

来自「verilog hdl经典例程」· RPT 代码 · 共 273 行 · 第 1/2 页

; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; seqdet.v                         ; yes             ; User Verilog HDL File  ; E:/lab/seqdet.v/seqdet.v     ;
+----------------------------------+-----------------+------------------------+------------------------------+


+---------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                   ;
+-----------------------------------------------+---------------+
; Resource                                      ; Usage         ;
+-----------------------------------------------+---------------+
; Estimated ALUTs Used                          ; 4             ;
; Dedicated logic registers                     ; 3             ;
;                                               ;               ;
; Estimated ALUTs Unavailable                   ; 2             ;
;                                               ;               ;
; Total combinational functions                 ; 4             ;
; Combinational ALUT usage by number of inputs  ;               ;
;     -- 7 input functions                      ; 0             ;
;     -- 6 input functions                      ; 0             ;
;     -- 5 input functions                      ; 3             ;
;     -- 4 input functions                      ; 1             ;
;     -- <=3 input functions                    ; 0             ;
;                                               ;               ;
; Combinational ALUTs by mode                   ;               ;
;     -- normal mode                            ; 4             ;
;     -- extended LUT mode                      ; 0             ;
;     -- arithmetic mode                        ; 0             ;
;     -- shared arithmetic mode                 ; 0             ;
;                                               ;               ;
; Estimated ALUT/register pairs used            ; 6             ;
;                                               ;               ;
; Total registers                               ; 3             ;
;     -- Dedicated logic registers              ; 3             ;
;     -- I/O registers                          ; 0             ;
;                                               ;               ;
; Estimated ALMs:  partially or completely used ; 3             ;
;                                               ;               ;
; I/O pins                                      ; 7             ;
; Maximum fan-out node                          ; state[0]~reg0 ;
; Maximum fan-out                               ; 5             ;
; Total fan-out                                 ; 29            ;
; Average fan-out                               ; 2.07          ;
+-----------------------------------------------+---------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |seqdet                    ; 4 (4)             ; 3 (3)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 7    ; 0            ; |seqdet             ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |seqdet ;
+----------------+----------------------------------+--------------------+
; Parameter Name ; Value                            ; Type               ;
+----------------+----------------------------------+--------------------+
; IDLE           ; 00000000000000000000000000000000 ; Unsigned Binary    ;
; A              ; 00000000000000000000000000000001 ; Unsigned Binary    ;
; B              ; 00000000000000000000000000000010 ; Unsigned Binary    ;
; C              ; 00000000000000000000000000000011 ; Unsigned Binary    ;
; D              ; 00000000000000000000000000000100 ; Unsigned Binary    ;
; E              ; 00000000000000000000000000000101 ; Unsigned Binary    ;
; F              ; 00000000000000000000000000000110 ; Unsigned Binary    ;
; G              ; 00000000000000000000000000000111 ; Unsigned Binary    ;
+----------------+----------------------------------+--------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Mon May 18 10:32:04 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seqdet -c seqdet
Info: Found 1 design units, including 1 entities, in source file seqdet.v
    Info: Found entity 1: seqdet
Info: Elaborating entity "seqdet" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at seqdet.v(12): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at seqdet.v(16): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(22): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(26): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(30): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(34): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(38): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(42): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(46): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(50): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(54): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(58): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(62): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(66): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(70): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at seqdet.v(72): truncated value with size 32 to match size of target (3)
Info: Generated suppressed messages file E:/lab/seqdet.v/seqdet.map.smsg
Info: Implemented 11 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 4 output pins
    Info: Implemented 4 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Peak virtual memory: 165 megabytes
    Info: Processing ended: Mon May 18 10:32:06 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/lab/seqdet.v/seqdet.map.smsg.