prev_cmp_alu.map.qmsg

verilog hdl经典例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 16 15:41:28 2009 " "Info: Processing started: Sat May 16 15:41:28 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alu -c alu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"'d\";  expecting an identifier, or \"module\", or \"macromodule\", or \"function\", or \"parameter\", or \"primitive\", or \"real\", or \"realtime\", or \"reg\", or \"specparam\", or \"supply0\", or \"task\", or \"time\", or \"tri\", or \"tri0\", or \"tri1\", or \"triand\", or \"trior\", or \"trireg\", or \"wand\", or \"wire\", or \"integer\", or \"config\", or \"localparam\", or \"(*\", or \"include\", or \"library\" alu.v(4) " "Error (10170): Verilog HDL syntax error at alu.v(4) near text \"'d\";  expecting an identifier, or \"module\", or \"macromodule\", or \"function\", or \"parameter\", or \"primitive\", or \"real\", or \"realtime\", or \"reg\", or \"specparam\", or \"supply0\", or \"task\", or \"time\", or \"tri\", or \"tri0\", or \"tri1\", or \"triand\", or \"trior\", or \"trireg\", or \"wand\", or \"wire\", or \"integer\", or \"config\", or \"localparam\", or \"(*\", or \"include\", or \"library\"" {  } { { "alu.v" "" { Text "E:/lab/alu/alu.v" 4 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file alu.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Error: Peak virtual memory: 159 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat May 16 15:41:29 2009 " "Error: Processing ended: Sat May 16 15:41:29 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}