alu.tan.qmsg

verilog hdl经典例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 16 15:41:55 2009 " "Info: Processing started: Sat May 16 15:41:55 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off alu -c alu --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off alu -c alu --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[2\] out\[3\] 10.360 ns Longest " "Info: Longest tpd from source pin \"b\[2\]\" to destination pin \"out\[3\]\" is 10.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns b\[2\] 1 PIN PIN_R7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_R7; Fanout = 3; PIN Node = 'b\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[2] } "NODE_NAME" } } { "alu.v" "" { Text "E:/lab/alu/alu.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.467 ns) + CELL(0.350 ns) 5.597 ns Add0~158 2 COMB LCCOMB_X14_Y1_N6 2 " "Info: 2: + IC(4.467 ns) + CELL(0.350 ns) = 5.597 ns; Loc. = LCCOMB_X14_Y1_N6; Fanout = 2; COMB Node = 'Add0~158'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.817 ns" { b[2] Add0~158 } "NODE_NAME" } } { "alu.v" "" { Text "E:/lab/alu/alu.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 5.722 ns Add0~161 3 COMB LCCOMB_X14_Y1_N8 1 " "Info: 3: + IC(0.000 ns) + CELL(0.125 ns) = 5.722 ns; Loc. = LCCOMB_X14_Y1_N8; Fanout = 1; COMB Node = 'Add0~161'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { Add0~158 Add0~161 } "NODE_NAME" } } { "alu.v" "" { Text "E:/lab/alu/alu.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.357 ns) 6.641 ns Mux4~6 4 COMB LCCOMB_X11_Y1_N30 1 " "Info: 4: + IC(0.562 ns) + CELL(0.357 ns) = 6.641 ns; Loc. = LCCOMB_X11_Y1_N30; Fanout = 1; COMB Node = 'Mux4~6'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.919 ns" { Add0~161 Mux4~6 } "NODE_NAME" } } { "alu.v" "" { Text "E:/lab/alu/alu.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.575 ns) + CELL(2.144 ns) 10.360 ns out\[3\] 5 PIN PIN_V3 0 " "Info: 5: + IC(1.575 ns) + CELL(2.144 ns) = 10.360 ns; Loc. = PIN_V3; Fanout = 0; PIN Node = 'out\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.719 ns" { Mux4~6 out[3] } "NODE_NAME" } } { "alu.v" "" { Text "E:/lab/alu/alu.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.756 ns ( 36.25 % ) " "Info: Total cell delay = 3.756 ns ( 36.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.604 ns ( 63.75 % ) " "Info: Total interconnect delay = 6.604 ns ( 63.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.360 ns" { b[2] Add0~158 Add0~161 Mux4~6 out[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.360 ns" { b[2] {} b[2]~combout {} Add0~158 {} Add0~161 {} Mux4~6 {} out[3] {} } { 0.000ns 0.000ns 4.467ns 0.000ns 0.562ns 1.575ns } { 0.000ns 0.780ns 0.350ns 0.125ns 0.357ns 2.144ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Peak virtual memory: 130 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 16 15:41:56 2009 " "Info: Processing ended: Sat May 16 15:41:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}