alt_u_div_m3f.tdf

verilog hdl经典例程

--alt_u_div DEVICE_FAMILY="Stratix II" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=5 WIDTH_N=32 WIDTH_Q=32 WIDTH_R=5 denominator numerator quotient remainder
--VERSION_BEGIN 8.0SP1 cbx_cycloneii 2008:06:02:292401 cbx_lpm_abs 2008:06:02:292401 cbx_lpm_add_sub 2008:06:02:292401 cbx_lpm_divide 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratix 2008:06:02:292401 cbx_stratixii 2008:06:02:292401 cbx_util_mgl 2008:06:02:292401  VERSION_END


-- Copyright (C) 1991-2008 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 209 
SUBDESIGN alt_u_div_m3f
( 
	denominator[4..0]	:	input;
	numerator[31..0]	:	input;
	quotient[31..0]	:	output;
	remainder[4..0]	:	output;
) 
VARIABLE
	add_sub_0_result_int[1..0]	:	WIRE;
	add_sub_0_cout	:	WIRE;
	add_sub_0_dataa[0..0]	:	WIRE;
	add_sub_0_datab[0..0]	:	WIRE;
	add_sub_0_result[0..0]	:	WIRE;
	add_sub_1_result_int[2..0]	:	WIRE;
	add_sub_1_cout	:	WIRE;
	add_sub_1_dataa[1..0]	:	WIRE;
	add_sub_1_datab[1..0]	:	WIRE;
	add_sub_1_result[1..0]	:	WIRE;
	add_sub_10_result_int[6..0]	:	WIRE;
	add_sub_10_cout	:	WIRE;
	add_sub_10_dataa[5..0]	:	WIRE;
	add_sub_10_datab[5..0]	:	WIRE;
	add_sub_10_result[5..0]	:	WIRE;
	add_sub_11_result_int[6..0]	:	WIRE;
	add_sub_11_cout	:	WIRE;
	add_sub_11_dataa[5..0]	:	WIRE;
	add_sub_11_datab[5..0]	:	WIRE;
	add_sub_11_result[5..0]	:	WIRE;
	add_sub_12_result_int[6..0]	:	WIRE;
	add_sub_12_cout	:	WIRE;
	add_sub_12_dataa[5..0]	:	WIRE;
	add_sub_12_datab[5..0]	:	WIRE;
	add_sub_12_result[5..0]	:	WIRE;
	add_sub_13_result_int[6..0]	:	WIRE;
	add_sub_13_cout	:	WIRE;
	add_sub_13_dataa[5..0]	:	WIRE;
	add_sub_13_datab[5..0]	:	WIRE;
	add_sub_13_result[5..0]	:	WIRE;
	add_sub_14_result_int[6..0]	:	WIRE;
	add_sub_14_cout	:	WIRE;
	add_sub_14_dataa[5..0]	:	WIRE;
	add_sub_14_datab[5..0]	:	WIRE;
	add_sub_14_result[5..0]	:	WIRE;
	add_sub_15_result_int[6..0]	:	WIRE;
	add_sub_15_cout	:	WIRE;
	add_sub_15_dataa[5..0]	:	WIRE;
	add_sub_15_datab[5..0]	:	WIRE;
	add_sub_15_result[5..0]	:	WIRE;
	add_sub_16_result_int[6..0]	:	WIRE;
	add_sub_16_cout	:	WIRE;
	add_sub_16_dataa[5..0]	:	WIRE;
	add_sub_16_datab[5..0]	:	WIRE;
	add_sub_16_result[5..0]	:	WIRE;
	add_sub_17_result_int[6..0]	:	WIRE;
	add_sub_17_cout	:	WIRE;
	add_sub_17_dataa[5..0]	:	WIRE;
	add_sub_17_datab[5..0]	:	WIRE;
	add_sub_17_result[5..0]	:	WIRE;
	add_sub_18_result_int[6..0]	:	WIRE;
	add_sub_18_cout	:	WIRE;
	add_sub_18_dataa[5..0]	:	WIRE;
	add_sub_18_datab[5..0]	:	WIRE;
	add_sub_18_result[5..0]	:	WIRE;
	add_sub_19_result_int[6..0]	:	WIRE;
	add_sub_19_cout	:	WIRE;
	add_sub_19_dataa[5..0]	:	WIRE;
	add_sub_19_datab[5..0]	:	WIRE;
	add_sub_19_result[5..0]	:	WIRE;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_20_result_int[6..0]	:	WIRE;
	add_sub_20_cout	:	WIRE;