tryfunct.sim.rpt

verilog hdl经典例程

; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      48.10 % ;
; Total nodes checked                                 ; 801          ;
; Total output ports checked                          ; 1605         ;
; Total output ports with complete 1/0-value coverage ; 772          ;
; Total output ports with no 1/0-value coverage       ; 722          ;
; Total output ports with no 1-value coverage         ; 780          ;
; Total output ports with no 0-value coverage         ; 775          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                      ;
+-------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                     ; Output Port Name                                                                                                              ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------+
; |tryfunct|result[0]~reg0                                                                                                      ; |tryfunct|result[0]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[1]~reg0                                                                                                      ; |tryfunct|result[1]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[2]~reg0                                                                                                      ; |tryfunct|result[2]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[3]~reg0                                                                                                      ; |tryfunct|result[3]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[4]~reg0                                                                                                      ; |tryfunct|result[4]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[5]~reg0                                                                                                      ; |tryfunct|result[5]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[6]~reg0                                                                                                      ; |tryfunct|result[6]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[7]~reg0                                                                                                      ; |tryfunct|result[7]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[8]~reg0                                                                                                      ; |tryfunct|result[8]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[9]~reg0                                                                                                      ; |tryfunct|result[9]~reg0                                                                                                      ; regout           ;
; |tryfunct|result[10]~reg0                                                                                                     ; |tryfunct|result[10]~reg0                                                                                                     ; regout           ;
; |tryfunct|result[11]~reg0                                                                                                     ; |tryfunct|result[11]~reg0                                                                                                     ; regout           ;
; |tryfunct|result[12]~reg0                                                                                                     ; |tryfunct|result[12]~reg0                                                                                                     ; regout           ;
; |tryfunct|result[13]~reg0                                                                                                     ; |tryfunct|result[13]~reg0                                                                                                     ; regout           ;
; |tryfunct|result[14]~reg0                                                                                                     ; |tryfunct|result[14]~reg0                                                                                                     ; regout           ;
; |tryfunct|result[17]~reg0                                                                                                     ; |tryfunct|result[17]~reg0                                                                                                     ; regout           ;