compare.tan.qmsg

verilog hdl经典例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 16 08:39:34 2009 " "Info: Processing started: Sat May 16 08:39:34 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off compare -c compare --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off compare -c compare --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b equal 9.777 ns Longest " "Info: Longest tpd from source pin \"b\" to destination pin \"equal\" is 9.777 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.827 ns) 0.827 ns b 1 PIN PIN_V12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_V12; Fanout = 1; PIN Node = 'b'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { b } "NODE_NAME" } } { "compare.v" "" { Text "E:/lab/compare.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.529 ns) + CELL(0.154 ns) 5.510 ns equal~0 2 COMB LCCOMB_X17_Y25_N2 1 " "Info: 2: + IC(4.529 ns) + CELL(0.154 ns) = 5.510 ns; Loc. = LCCOMB_X17_Y25_N2; Fanout = 1; COMB Node = 'equal~0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.683 ns" { b equal~0 } "NODE_NAME" } } { "compare.v" "" { Text "E:/lab/compare.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.315 ns) + CELL(1.952 ns) 9.777 ns equal 3 PIN PIN_V11 0 " "Info: 3: + IC(2.315 ns) + CELL(1.952 ns) = 9.777 ns; Loc. = PIN_V11; Fanout = 0; PIN Node = 'equal'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.267 ns" { equal~0 equal } "NODE_NAME" } } { "compare.v" "" { Text "E:/lab/compare.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.933 ns ( 30.00 % ) " "Info: Total cell delay = 2.933 ns ( 30.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.844 ns ( 70.00 % ) " "Info: Total interconnect delay = 6.844 ns ( 70.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.777 ns" { b equal~0 equal } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.777 ns" { b {} b~combout {} equal~0 {} equal {} } { 0.000ns 0.000ns 4.529ns 2.315ns } { 0.000ns 0.827ns 0.154ns 1.952ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Peak virtual memory: 130 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 16 08:39:35 2009 " "Info: Processing ended: Sat May 16 08:39:35 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}