compare

来自「verilog hdl经典例程」· 代码 · 共 18 行

`timescale 1ns/ns
`include "./compare.v"
module comparetest;
reg a,b;
wire equal;
initial
begin a=0;
      b=0;
#100 a=0;
b=1;
#100 a=1;
     b=1; 
#100 a=1;
     b=0;
#100 $stop;
end
compare compare1(.equal(equal),.a(a),.b(b));
endmodule