half_clk.tan.rpt

verilog hdl经典例程

+-------+--------------+------------+-------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To           ; To Clock ;
+-------+--------------+------------+-------+--------------+----------+
; N/A   ; None         ; 3.449 ns   ; reset ; clk_out~reg0 ; clk_in   ;
+-------+--------------+------------+-------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 4.904 ns   ; clk_out~reg0 ; clk_out ; clk_in     ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -3.210 ns ; reset ; clk_out~reg0 ; clk_in   ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Sat May 16 10:40:18 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off half_clk -c half_clk --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_in" is an undefined clock
Info: Clock "clk_in" Internal fmax is restricted to 500.0 MHz between source register "clk_out~reg0" and destination register "clk_out~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.396 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
            Info: 2: + IC(0.000 ns) + CELL(0.241 ns) = 0.241 ns; Loc. = LCCOMB_X38_Y2_N18; Fanout = 1; COMB Node = 'clk_out~13'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.396 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
            Info: Total cell delay = 0.396 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk_in" to destination register is 2.190 ns
                Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'
                Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 1.448 ns ( 66.12 % )
                Info: Total interconnect delay = 0.742 ns ( 33.88 % )
            Info: - Longest clock path from clock "clk_in" to source register is 2.190 ns
                Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'
                Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
                Info: Total cell delay = 1.448 ns ( 66.12 % )
                Info: Total interconnect delay = 0.742 ns ( 33.88 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "clk_out~reg0" (data pin = "reset", clock pin = "clk_in") is 3.449 ns
    Info: + Longest pin to register delay is 5.549 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_G8; Fanout = 1; PIN Node = 'reset'
        Info: 2: + IC(4.534 ns) + CELL(0.053 ns) = 5.394 ns; Loc. = LCCOMB_X38_Y2_N18; Fanout = 1; COMB Node = 'clk_out~13'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.549 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.015 ns ( 18.29 % )
        Info: Total interconnect delay = 4.534 ns ( 81.71 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk_in" to destination register is 2.190 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.448 ns ( 66.12 % )
        Info: Total interconnect delay = 0.742 ns ( 33.88 % )
Info: tco from clock "clk_in" to destination pin "clk_out" through register "clk_out~reg0" is 4.904 ns
    Info: + Longest clock path from clock "clk_in" to source register is 2.190 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.448 ns ( 66.12 % )
        Info: Total interconnect delay = 0.742 ns ( 33.88 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 2.620 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: 2: + IC(0.678 ns) + CELL(1.942 ns) = 2.620 ns; Loc. = PIN_T9; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 1.942 ns ( 74.12 % )
        Info: Total interconnect delay = 0.678 ns ( 25.88 % )
Info: th for register "clk_out~reg0" (data pin = "reset", clock pin = "clk_in") is -3.210 ns
    Info: + Longest clock path from clock "clk_in" to destination register is 2.190 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'
        Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.448 ns ( 66.12 % )
        Info: Total interconnect delay = 0.742 ns ( 33.88 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.549 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_G8; Fanout = 1; PIN Node = 'reset'
        Info: 2: + IC(4.534 ns) + CELL(0.053 ns) = 5.394 ns; Loc. = LCCOMB_X38_Y2_N18; Fanout = 1; COMB Node = 'clk_out~13'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.549 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'
        Info: Total cell delay = 1.015 ns ( 18.29 % )
        Info: Total interconnect delay = 4.534 ns ( 81.71 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 130 megabytes
    Info: Processing ended: Sat May 16 10:40:19 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01