half_clk.tan.qmsg

来自「verilog hdl经典例程」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_in register register clk_out~reg0 clk_out~reg0 500.0 MHz Internal " "Info: Clock \"clk_in\" Internal fmax is restricted to 500.0 MHz between source register \"clk_out~reg0\" and destination register \"clk_out~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.396 ns + Longest register register " "Info: + Longest register to register delay is 0.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LCFF_X38_Y2_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.241 ns) 0.241 ns clk_out~13 2 COMB LCCOMB_X38_Y2_N18 1 " "Info: 2: + IC(0.000 ns) + CELL(0.241 ns) = 0.241 ns; Loc. = LCCOMB_X38_Y2_N18; Fanout = 1; COMB Node = 'clk_out~13'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.241 ns" { clk_out~reg0 clk_out~13 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.396 ns clk_out~reg0 3 REG LCFF_X38_Y2_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.396 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.396 ns ( 100.00 % ) " "Info: Total cell delay = 0.396 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { clk_out~reg0 clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.396 ns" { clk_out~reg0 {} clk_out~13 {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.241ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.190 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 2.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns clk_in 1 CLK PIN_W1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(0.618 ns) 2.190 ns clk_out~reg0 2 REG LCFF_X38_Y2_N19 2 " "Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 66.12 % ) " "Info: Total cell delay = 1.448 ns ( 66.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.742 ns ( 33.88 % ) " "Info: Total interconnect delay = 0.742 ns ( 33.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.190 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 2.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns clk_in 1 CLK PIN_W1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(0.618 ns) 2.190 ns clk_out~reg0 2 REG LCFF_X38_Y2_N19 2 " "Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 66.12 % ) " "Info: Total cell delay = 1.448 ns ( 66.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.742 ns ( 33.88 % ) " "Info: Total interconnect delay = 0.742 ns ( 33.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { clk_out~reg0 clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.396 ns" { clk_out~reg0 {} clk_out~13 {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.241ns 0.155ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { clk_out~reg0 {} } {  } {  } "" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "clk_out~reg0 reset clk_in 3.449 ns register " "Info: tsu for register \"clk_out~reg0\" (data pin = \"reset\", clock pin = \"clk_in\") is 3.449 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.549 ns + Longest pin register " "Info: + Longest pin to register delay is 5.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns reset 1 PIN PIN_G8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_G8; Fanout = 1; PIN Node = 'reset'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.534 ns) + CELL(0.053 ns) 5.394 ns clk_out~13 2 COMB LCCOMB_X38_Y2_N18 1 " "Info: 2: + IC(4.534 ns) + CELL(0.053 ns) = 5.394 ns; Loc. = LCCOMB_X38_Y2_N18; Fanout = 1; COMB Node = 'clk_out~13'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.587 ns" { reset clk_out~13 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.549 ns clk_out~reg0 3 REG LCFF_X38_Y2_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.549 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.015 ns ( 18.29 % ) " "Info: Total cell delay = 1.015 ns ( 18.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.534 ns ( 81.71 % ) " "Info: Total interconnect delay = 4.534 ns ( 81.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.549 ns" { reset clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.549 ns" { reset {} reset~combout {} clk_out~13 {} clk_out~reg0 {} } { 0.000ns 0.000ns 4.534ns 0.000ns } { 0.000ns 0.807ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.190 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 2.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns clk_in 1 CLK PIN_W1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(0.618 ns) 2.190 ns clk_out~reg0 2 REG LCFF_X38_Y2_N19 2 " "Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 66.12 % ) " "Info: Total cell delay = 1.448 ns ( 66.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.742 ns ( 33.88 % ) " "Info: Total interconnect delay = 0.742 ns ( 33.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.549 ns" { reset clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.549 ns" { reset {} reset~combout {} clk_out~13 {} clk_out~reg0 {} } { 0.000ns 0.000ns 4.534ns 0.000ns } { 0.000ns 0.807ns 0.053ns 0.155ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in clk_out clk_out~reg0 4.904 ns register " "Info: tco from clock \"clk_in\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 4.904 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.190 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 2.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns clk_in 1 CLK PIN_W1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(0.618 ns) 2.190 ns clk_out~reg0 2 REG LCFF_X38_Y2_N19 2 " "Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 66.12 % ) " "Info: Total cell delay = 1.448 ns ( 66.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.742 ns ( 33.88 % ) " "Info: Total interconnect delay = 0.742 ns ( 33.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.620 ns + Longest register pin " "Info: + Longest register to pin delay is 2.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LCFF_X38_Y2_N19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.678 ns) + CELL(1.942 ns) 2.620 ns clk_out 2 PIN PIN_T9 0 " "Info: 2: + IC(0.678 ns) + CELL(1.942 ns) = 2.620 ns; Loc. = PIN_T9; Fanout = 0; PIN Node = 'clk_out'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.620 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.942 ns ( 74.12 % ) " "Info: Total cell delay = 1.942 ns ( 74.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.678 ns ( 25.88 % ) " "Info: Total interconnect delay = 0.678 ns ( 25.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.620 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.620 ns" { clk_out~reg0 {} clk_out {} } { 0.000ns 0.678ns } { 0.000ns 1.942ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.620 ns" { clk_out~reg0 clk_out } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.620 ns" { clk_out~reg0 {} clk_out {} } { 0.000ns 0.678ns } { 0.000ns 1.942ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "clk_out~reg0 reset clk_in -3.210 ns register " "Info: th for register \"clk_out~reg0\" (data pin = \"reset\", clock pin = \"clk_in\") is -3.210 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.190 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 2.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns clk_in 1 CLK PIN_W1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_W1; Fanout = 1; CLK Node = 'clk_in'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.742 ns) + CELL(0.618 ns) 2.190 ns clk_out~reg0 2 REG LCFF_X38_Y2_N19 2 " "Info: 2: + IC(0.742 ns) + CELL(0.618 ns) = 2.190 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.360 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 66.12 % ) " "Info: Total cell delay = 1.448 ns ( 66.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.742 ns ( 33.88 % ) " "Info: Total interconnect delay = 0.742 ns ( 33.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.549 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns reset 1 PIN PIN_G8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_G8; Fanout = 1; PIN Node = 'reset'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.534 ns) + CELL(0.053 ns) 5.394 ns clk_out~13 2 COMB LCCOMB_X38_Y2_N18 1 " "Info: 2: + IC(4.534 ns) + CELL(0.053 ns) = 5.394 ns; Loc. = LCCOMB_X38_Y2_N18; Fanout = 1; COMB Node = 'clk_out~13'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.587 ns" { reset clk_out~13 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.549 ns clk_out~reg0 3 REG LCFF_X38_Y2_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.549 ns; Loc. = LCFF_X38_Y2_N19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 5 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.015 ns ( 18.29 % ) " "Info: Total cell delay = 1.015 ns ( 18.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.534 ns ( 81.71 % ) " "Info: Total interconnect delay = 4.534 ns ( 81.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.549 ns" { reset clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.549 ns" { reset {} reset~combout {} clk_out~13 {} clk_out~reg0 {} } { 0.000ns 0.000ns 4.534ns 0.000ns } { 0.000ns 0.807ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.190 ns" { clk_in clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.190 ns" { clk_in {} clk_in~combout {} clk_out~reg0 {} } { 0.000ns 0.000ns 0.742ns } { 0.000ns 0.830ns 0.618ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.549 ns" { reset clk_out~13 clk_out~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.549 ns" { reset {} reset~combout {} clk_out~13 {} clk_out~reg0 {} } { 0.000ns 0.000ns 4.534ns 0.000ns } { 0.000ns 0.807ns 0.053ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}