half_clk.map.summary

来自「verilog hdl经典例程」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Sat May 16 10:40:07 2009
Quartus II Version : 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
Revision Name : half_clk
Top-level Entity Name : half_clk
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 1
    Dedicated logic registers : 1
Total registers : 1
Total pins : 3
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0