half_clk.tan.summary

来自「verilog hdl经典例程」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.449 ns
From           : reset
To             : clk_out~reg0
From Clock     : --
To Clock       : clk_in
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.904 ns
From           : clk_out~reg0
To             : clk_out
From Clock     : clk_in
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.210 ns
From           : reset
To             : clk_out~reg0
From Clock     : --
To Clock       : clk_in
Failed Paths   : 0

Type           : Clock Setup: 'clk_in'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 500.00 MHz ( period = 2.000 ns )
From           : clk_out~reg0
To             : clk_out~reg0
From Clock     : clk_in
To Clock       : clk_in
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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