half_clk_tb.v.bak

verilog hdl经典例程

`timescale 1ns/100ps
`define clk_cycle 50
module half_clk_tb;
reg clk,reset;
wire clk_out;
always # clk_cycle clk=~clk;
initial
begin
 clk=0;
 reset=1;
 #100 reset=0;
 #100 reset=1;
 #10000 $stop;
end
half_clk half_clk(.reset(reset),.clk_in(clk),.clk_out(clk_out));
endmodule