s_to_p.v

verilog hdl经典例程

module s_to_p(T1,data,D_out,DSC,TAKE,ADD_101);
output T1;
output [7:0] data;
input D_out,DSC,TAKE,ADD_101;
wire [7:0] data;
wire T1,clk2;
reg [7:0] data_latch,data_latch_buf;
assign clk2=DSC&TAKE;
assign T1=!clk2;
assign data=(!ADD_101)?data_latch:8'bz;
always@(posedge clk2)
begin
  data_latch_buf=data_latch<<1;
  data_latch=data_latch_buf;
  data_latch[0]=D_out;
end
endmodule