block.tan.rpt

来自「verilog hdl经典例程」· RPT 代码 · 共 223 行 · 第 1/2 页

+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 6.993 ns   ; b[2]~reg0 ; b[2] ; clk        ;
; N/A   ; None         ; 6.167 ns   ; c[3]~reg0 ; c[3] ; clk        ;
; N/A   ; None         ; 6.145 ns   ; b[0]~reg0 ; b[0] ; clk        ;
; N/A   ; None         ; 6.062 ns   ; c[0]~reg0 ; c[0] ; clk        ;
; N/A   ; None         ; 6.053 ns   ; b[1]~reg0 ; b[1] ; clk        ;
; N/A   ; None         ; 5.745 ns   ; c[1]~reg0 ; c[1] ; clk        ;
; N/A   ; None         ; 5.388 ns   ; c[2]~reg0 ; c[2] ; clk        ;
; N/A   ; None         ; 5.113 ns   ; b[3]~reg0 ; b[3] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -2.528 ns ; a[1] ; b[1]~reg0 ; clk      ;
; N/A           ; None        ; -2.595 ns ; a[0] ; b[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.885 ns ; a[2] ; b[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.506 ns ; a[3] ; b[3]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
    Info: Processing started: Mon May 18 09:37:15 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off block -c block --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "b[0]~reg0" and destination register "c[0]~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.415 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y12_N17; Fanout = 2; REG Node = 'b[0]~reg0'
            Info: 2: + IC(0.207 ns) + CELL(0.053 ns) = 0.260 ns; Loc. = LCCOMB_X22_Y12_N18; Fanout = 1; COMB Node = 'c[0]~reg0feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.415 ns; Loc. = LCFF_X22_Y12_N19; Fanout = 1; REG Node = 'c[0]~reg0'
            Info: Total cell delay = 0.208 ns ( 50.12 % )
            Info: Total interconnect delay = 0.207 ns ( 49.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.483 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.668 ns) + CELL(0.618 ns) = 2.483 ns; Loc. = LCFF_X22_Y12_N19; Fanout = 1; REG Node = 'c[0]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.28 % )
                Info: Total interconnect delay = 1.011 ns ( 40.72 % )
            Info: - Longest clock path from clock "clk" to source register is 2.483 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.668 ns) + CELL(0.618 ns) = 2.483 ns; Loc. = LCFF_X22_Y12_N17; Fanout = 2; REG Node = 'b[0]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.28 % )
                Info: Total interconnect delay = 1.011 ns ( 40.72 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "b[3]~reg0" (data pin = "a[3]", clock pin = "clk") is 3.745 ns
    Info: + Longest pin to register delay is 6.139 ns
        Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_H20; Fanout = 1; PIN Node = 'a[3]'
        Info: 2: + IC(5.020 ns) + CELL(0.309 ns) = 6.139 ns; Loc. = LCFF_X30_Y3_N17; Fanout = 2; REG Node = 'b[3]~reg0'
        Info: Total cell delay = 1.119 ns ( 18.23 % )
        Info: Total interconnect delay = 5.020 ns ( 81.77 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.484 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.669 ns) + CELL(0.618 ns) = 2.484 ns; Loc. = LCFF_X30_Y3_N17; Fanout = 2; REG Node = 'b[3]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.26 % )
        Info: Total interconnect delay = 1.012 ns ( 40.74 % )
Info: tco from clock "clk" to destination pin "b[2]" through register "b[2]~reg0" is 6.993 ns
    Info: + Longest clock path from clock "clk" to source register is 2.476 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.661 ns) + CELL(0.618 ns) = 2.476 ns; Loc. = LCFF_X21_Y21_N17; Fanout = 2; REG Node = 'b[2]~reg0'
        Info: Total cell delay = 1.472 ns ( 59.45 % )
        Info: Total interconnect delay = 1.004 ns ( 40.55 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 4.423 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y21_N17; Fanout = 2; REG Node = 'b[2]~reg0'
        Info: 2: + IC(2.461 ns) + CELL(1.962 ns) = 4.423 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'b[2]'
        Info: Total cell delay = 1.962 ns ( 44.36 % )
        Info: Total interconnect delay = 2.461 ns ( 55.64 % )
Info: th for register "b[1]~reg0" (data pin = "a[1]", clock pin = "clk") is -2.528 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.497 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X26_Y25_N17; Fanout = 2; REG Node = 'b[1]~reg0'
        Info: Total cell delay = 1.472 ns ( 58.95 % )
        Info: Total interconnect delay = 1.025 ns ( 41.05 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.174 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H9; Fanout = 1; PIN Node = 'a[1]'
        Info: 2: + IC(4.159 ns) + CELL(0.053 ns) = 5.019 ns; Loc. = LCCOMB_X26_Y25_N16; Fanout = 1; COMB Node = 'b[1]~reg0feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.174 ns; Loc. = LCFF_X26_Y25_N17; Fanout = 2; REG Node = 'b[1]~reg0'
        Info: Total cell delay = 1.015 ns ( 19.62 % )
        Info: Total interconnect delay = 4.159 ns ( 80.38 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 130 megabytes
    Info: Processing ended: Mon May 18 09:37:16 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01