count__10.fit.summary

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

Fitter Status : Successful - Sun Mar 29 12:18:44 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : count__10
Top-level Entity Name : count__10
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 10 / 10,570 ( < 1 % )
Total pins : 14 / 336 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )