💻 这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢. - 源码文件列表

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源码文件总数： 50 个
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1
📄 count__10.qpf
905 B
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2
📄 count__10.tan.summary
1.64 KB
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3
📄 count__10.vwf
6.89 KB
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4
📄 count__10.qsf
1.7 KB
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5
📄 count__10.done
26 B
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6
📄 count__10.tan.rpt
21.69 KB
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7
📄 count__10.map.summary
364 B
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8
📄 count__10.qws
611 B
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9
📄 count__10.rtlv.hdb
0 B
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10
📄 count__10.sgdiff.cdb
0 B
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11
📄 count__10.rtlv_sg.cdb
0 B
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12
📄 count__10.signalprobe.cdb
0 B
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13
📄 count__10.cmp.rdb
0 B
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14
📄 add_sub_1sh.tdf
2.37 KB
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15
📄 count__10.cmp.hdb
0 B
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16
📄 count__10.sim.vwf
7.1 KB
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17
📄 count__10.syn_hier_info
0 B
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18
📄 count__10.map.logdb
4 B
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19
📄 count__10.sim.hdb
0 B
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20
📄 count__10.fnsim.hdb
0 B
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21
📄 count__10.(0).cnf.hdb
0 B
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22
📄 count__10.fnsim.qmsg
13.21 KB
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23
📄 count__10.cmp0.ddb
0 B
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24
📄 count__10.cmp.cdb
0 B
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25
📄 count__10.asm.qmsg
1.69 KB
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26
📄 count__10.sgdiff.hdb
0 B
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27
📄 count__10.hif
577 B
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28
📄 count__10.fit.qmsg
25.89 KB
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29
📄 count__10.cmp.kpt
209 B
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30
📄 count__10.db_info
135 B
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31
📄 count__10.psp
0 B
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32
📄 count__10.sld_design_entry_dsc.sci
0 B
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33
📄 count__10.dbp
0 B
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34
📄 count__10.sld_design_entry.sci
0 B
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35
📄 count__10.eco.cdb
0 B
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36
📄 count__10.cmp.tdb
0 B
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37
📄 count__10.hier_info
866 B
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38
📄 count__10.fnsim.cdb
0 B
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39
📝 count__10.cbx.xml
188 B
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40
📄 count__10.tan.qmsg
32.02 KB
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41
📄 count__10.sim.qmsg
3.08 KB
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42
📄 count__10.sim.rdb
0 B
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43
📄 count__10.map.hdb
0 B
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44
📄 count__10.map.cdb
0 B
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45
📄 count__10.(0).cnf.cdb
0 B
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46
📄 count__10.map.qmsg
3.9 KB
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47
📄 wed.zsf
145 B
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48
📄 count__10.rtlv_sg_swap.cdb
0 B
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49
📄 count__10.eds_overflow
3 B
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50
📄 count__10.cmp.logdb
4 B
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