count__10.v

来自「这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.」· Verilog 代码 · 共 20 行

module count__10(cin,clk,cout,qout,cout,data,load,reset);
input cin,clk,load,reset;
output cout;
output [3:0] qout;
input [3:0] data;
reg [3:0] qout;
always @(posedge clk or negedge reset)
begin
if(!reset) qout=0;
else if(load) qout=data;
else if(cin)
begin
   if(qout[3:0]==9)
   begin qout[3:0]=0;
end
   else qout[3:0]=qout[3:0]+1;
end
end
assign cout=((qout[3:0]==9)&cin)?1:0;
endmodule