count__10.map.rpt

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                      ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                  ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------+
; count__10.v                      ; yes             ; User Verilog HDL File  ; E:/quartus6.0/my_desgin/count__10/count__10.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+---------------------------------------------+--------------+
; Resource                                    ; Usage        ;
+---------------------------------------------+--------------+
; Total logic elements                        ; 10           ;
;     -- Combinational with no register       ; 6            ;
;     -- Register only                        ; 0            ;
;     -- Combinational with a register        ; 4            ;
;                                             ;              ;
; Logic element usage by number of LUT inputs ;              ;
;     -- 4 input functions                    ; 5            ;
;     -- 3 input functions                    ; 1            ;
;     -- 2 input functions                    ; 4            ;
;     -- 1 input functions                    ; 0            ;
;     -- 0 input functions                    ; 0            ;
;         -- Combinational cells for routing  ; 0            ;
;                                             ;              ;
; Logic elements by mode                      ;              ;
;     -- normal mode                          ; 10           ;
;     -- arithmetic mode                      ; 0            ;
;     -- qfbk mode                            ; 0            ;
;     -- register cascade mode                ; 0            ;
;     -- synchronous clear/load mode          ; 0            ;
;     -- asynchronous clear/load mode         ; 4            ;
;                                             ;              ;
; Total registers                             ; 4            ;
; I/O pins                                    ; 14           ;
; Maximum fan-out node                        ; qout[0]~reg0 ;
; Maximum fan-out                             ; 6            ;
; Total fan-out                               ; 49           ;
; Average fan-out                             ; 2.04         ;
+---------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |count__10                 ; 10 (10)     ; 4            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 14   ; 0            ; 6 (6)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |count__10          ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |count__10|qout[2]~reg0    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Mar 29 12:18:36 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count__10 -c count__10
Info: Found 1 design units, including 1 entities, in source file count__10.v
    Info: Found entity 1: count__10
Info: Elaborating entity "count__10" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at count__10.v(16): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at count__10.v(19): truncated value with size 32 to match size of target (1)
Warning (10136): Verilog HDL Module Declaration warning at count__10.v(1): port "cout" already exists in the list of ports
Info: Implemented 24 device resources after synthesis - the final resource count might be different
    Info: Implemented 8 input pins
    Info: Implemented 6 output pins
    Info: Implemented 10 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Sun Mar 29 12:18:36 2009
    Info: Elapsed time: 00:00:00