📄 count__10.sim.rpt
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; |count__10|lpm_add_sub:Add0|addcore:adder|_~4 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~5 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~6 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~7 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~7 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~8 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~8 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~10 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~10 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~11 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~11 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~13 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~13 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~14 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~14 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; |count__10|qout~0 ; |count__10|qout~0 ; out ;
; |count__10|qout~4 ; |count__10|qout~4 ; out ;
; |count__10|qout~8 ; |count__10|qout~8 ; out ;
; |count__10|qout[2]~reg0 ; |count__10|qout[2]~reg0 ; out ;
; |count__10|cout~0 ; |count__10|cout~0 ; out0 ;
; |count__10|qout[3]~reg0 ; |count__10|qout[3]~reg0 ; out ;
; |count__10|cin ; |count__10|cin ; out ;
; |count__10| renamed_port_1 ; |count__10| renamed_port_1 ; pin_out ;
; |count__10|qout[2] ; |count__10|qout[2] ; pin_out ;
; |count__10|qout[3] ; |count__10|qout[3] ; pin_out ;
; |count__10|cout ; |count__10|cout ; pin_out ;
; |count__10|data[0] ; |count__10|data[0] ; out ;
; |count__10|data[1] ; |count__10|data[1] ; out ;
; |count__10|data[2] ; |count__10|data[2] ; out ;
; |count__10|data[3] ; |count__10|data[3] ; out ;
; |count__10|load ; |count__10|load ; out ;
; |count__10|Equal0~33 ; |count__10|Equal0~33 ; out0 ;
; |count__10|lpm_add_sub:Add0|result_node[3] ; |count__10|lpm_add_sub:Add0|result_node[3] ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0] ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~1 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~1 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~2 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~2 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3] ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[2] ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[1] ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3] ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~4 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~4 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~5 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~5 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~6 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~6 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~7 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~7 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~8 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~8 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~10 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~10 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~11 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~11 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~13 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~13 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~14 ; |count__10|lpm_add_sub:Add0|addcore:adder|_~14 ; out0 ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; sout ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
Info: Processing started: Sun Mar 29 12:20:25 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off count__10 -c count__10
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 45.21 %
Info: Number of transitions in simulation is 275
Info: Vector file count__10.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Mar 29 12:20:26 2009
Info: Elapsed time: 00:00:01
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