count__10.sim.rpt

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      45.21 % ;
; Total nodes checked                                 ; 70           ;
; Total output ports checked                          ; 73           ;
; Total output ports with complete 1/0-value coverage ; 33           ;
; Total output ports with no 1/0-value coverage       ; 40           ;
; Total output ports with no 1-value coverage         ; 40           ;
; Total output ports with no 0-value coverage         ; 40           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                   ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; Node Name                                                                 ; Output Port Name                                                               ; Output Port Type ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; |count__10|qout~1                                                         ; |count__10|qout~1                                                              ; out              ;
; |count__10|qout~2                                                         ; |count__10|qout~2                                                              ; out              ;
; |count__10|qout~3                                                         ; |count__10|qout~3                                                              ; out              ;
; |count__10|qout~5                                                         ; |count__10|qout~5                                                              ; out              ;
; |count__10|qout~6                                                         ; |count__10|qout~6                                                              ; out              ;
; |count__10|qout~7                                                         ; |count__10|qout~7                                                              ; out              ;
; |count__10|qout~9                                                         ; |count__10|qout~9                                                              ; out              ;
; |count__10|qout~10                                                        ; |count__10|qout~10                                                             ; out              ;
; |count__10|qout~11                                                        ; |count__10|qout~11                                                             ; out              ;
; |count__10|qout[1]~reg0                                                   ; |count__10|qout[1]~reg0                                                        ; out              ;
; |count__10|qout[0]~reg0                                                   ; |count__10|qout[0]~reg0                                                        ; out              ;
; |count__10|clk                                                            ; |count__10|clk                                                                 ; out              ;
; |count__10|qout[0]                                                        ; |count__10|qout[0]                                                             ; pin_out          ;
; |count__10|qout[1]                                                        ; |count__10|qout[1]                                                             ; pin_out          ;
; |count__10|reset                                                          ; |count__10|reset                                                               ; out              ;
; |count__10|lpm_add_sub:Add0|result_node[0]                                ; |count__10|lpm_add_sub:Add0|result_node[0]                                     ; out0             ;
; |count__10|lpm_add_sub:Add0|result_node[1]                                ; |count__10|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |count__10|lpm_add_sub:Add0|result_node[2]                                ; |count__10|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~0                             ; |count__10|lpm_add_sub:Add0|addcore:adder|_~0                                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~3                             ; |count__10|lpm_add_sub:Add0|addcore:adder|_~3                                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3             ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~3                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]               ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]               ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~9                             ; |count__10|lpm_add_sub:Add0|addcore:adder|_~9                                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~12                            ; |count__10|lpm_add_sub:Add0|addcore:adder|_~12                                 ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~15                            ; |count__10|lpm_add_sub:Add0|addcore:adder|_~15                                 ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]      ; cout             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |count__10|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; sout             ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                      ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; Node Name                                                                 ; Output Port Name                                                               ; Output Port Type ;
+---------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------------+
; |count__10|qout~0                                                         ; |count__10|qout~0                                                              ; out              ;
; |count__10|qout~4                                                         ; |count__10|qout~4                                                              ; out              ;
; |count__10|qout~8                                                         ; |count__10|qout~8                                                              ; out              ;
; |count__10|qout[2]~reg0                                                   ; |count__10|qout[2]~reg0                                                        ; out              ;
; |count__10|cout~0                                                         ; |count__10|cout~0                                                              ; out0             ;
; |count__10|qout[3]~reg0                                                   ; |count__10|qout[3]~reg0                                                        ; out              ;
; |count__10|cin                                                            ; |count__10|cin                                                                 ; out              ;
; |count__10| renamed_port_1                                                ; |count__10| renamed_port_1                                                     ; pin_out          ;
; |count__10|qout[2]                                                        ; |count__10|qout[2]                                                             ; pin_out          ;
; |count__10|qout[3]                                                        ; |count__10|qout[3]                                                             ; pin_out          ;
; |count__10|cout                                                           ; |count__10|cout                                                                ; pin_out          ;
; |count__10|data[0]                                                        ; |count__10|data[0]                                                             ; out              ;
; |count__10|data[1]                                                        ; |count__10|data[1]                                                             ; out              ;
; |count__10|data[2]                                                        ; |count__10|data[2]                                                             ; out              ;
; |count__10|data[3]                                                        ; |count__10|data[3]                                                             ; out              ;
; |count__10|load                                                           ; |count__10|load                                                                ; out              ;
; |count__10|Equal0~33                                                      ; |count__10|Equal0~33                                                           ; out0             ;
; |count__10|lpm_add_sub:Add0|result_node[3]                                ; |count__10|lpm_add_sub:Add0|result_node[3]                                     ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0                 ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0                      ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0]                   ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[0]                        ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~1                             ; |count__10|lpm_add_sub:Add0|addcore:adder|_~1                                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|_~2                             ; |count__10|lpm_add_sub:Add0|addcore:adder|_~2                                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1                 ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3]~1                      ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3]                   ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[3]                        ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[2]                   ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[2]                        ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[1]                   ; |count__10|lpm_add_sub:Add0|addcore:adder|datab_node[1]                        ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1             ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]~1                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2             ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~2                  ; out0             ;
; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]               ; |count__10|lpm_add_sub:Add0|addcore:adder|unreg_res_node[3]                    ; out0             ;