count__10.map.qmsg

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 29 12:18:36 2009 " "Info: Processing started: Sun Mar 29 12:18:36 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off count__10 -c count__10 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count__10 -c count__10" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count__10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file count__10.v" { { "Info" "ISGN_ENTITY_NAME" "1 count__10 " "Info: Found entity 1: count__10" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "count__10 " "Info: Elaborating entity \"count__10\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 count__10.v(16) " "Warning (10230): Verilog HDL assignment warning at count__10.v(16): truncated value with size 32 to match size of target (4)" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 count__10.v(19) " "Warning (10230): Verilog HDL assignment warning at count__10.v(19): truncated value with size 32 to match size of target (1)" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_PORT_IS_ALREADY_DEFINED_WARNING" "cout count__10.v(1) " "Warning (10136): Verilog HDL Module Declaration warning at count__10.v(1): port \"cout\" already exists in the list of ports" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 1 0 0 } }  } 0 10136 "Verilog HDL Module Declaration warning at %2!s!: port \"%1!s!\" already exists in the list of ports" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "24 " "Info: Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "10 " "Info: Implemented 10 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 12:18:36 2009 " "Info: Processing ended: Sun Mar 29 12:18:36 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}