count__10.tan.qmsg

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register qout\[0\]~reg0 qout\[3\]~reg0 422.12 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 422.12 MHz between source register \"qout\[0\]~reg0\" and destination register \"qout\[3\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.454 ns + Longest register register " "Info: + Longest register to register delay is 1.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qout\[0\]~reg0 1 REG LC_X41_Y30_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.366 ns) 0.798 ns cout~27 2 COMB LC_X41_Y30_N7 3 " "Info: 2: + IC(0.432 ns) + CELL(0.366 ns) = 0.798 ns; Loc. = LC_X41_Y30_N7; Fanout = 3; COMB Node = 'cout~27'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.798 ns" { qout[0]~reg0 cout~27 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.319 ns) 1.454 ns qout\[3\]~reg0 3 REG LC_X41_Y30_N1 3 " "Info: 3: + IC(0.337 ns) + CELL(0.319 ns) = 1.454 ns; Loc. = LC_X41_Y30_N1; Fanout = 3; REG Node = 'qout\[3\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.656 ns" { cout~27 qout[3]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.685 ns ( 47.11 % ) " "Info: Total cell delay = 0.685 ns ( 47.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.769 ns ( 52.89 % ) " "Info: Total interconnect delay = 0.769 ns ( 52.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.454 ns" { qout[0]~reg0 cout~27 qout[3]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "1.454 ns" { qout[0]~reg0 cout~27 qout[3]~reg0 } { 0.000ns 0.432ns 0.337ns } { 0.000ns 0.366ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.872 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns qout\[3\]~reg0 2 REG LC_X41_Y30_N1 3 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N1; Fanout = 3; REG Node = 'qout\[3\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.044 ns" { clk qout[3]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[3]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[3]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.872 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns qout\[0\]~reg0 2 REG LC_X41_Y30_N4 6 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.044 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[3]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[3]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.454 ns" { qout[0]~reg0 cout~27 qout[3]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "1.454 ns" { qout[0]~reg0 cout~27 qout[3]~reg0 } { 0.000ns 0.432ns 0.337ns } { 0.000ns 0.366ns 0.319ns } } } { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[3]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[3]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { qout[3]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "" { qout[3]~reg0 } {  } {  } } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "qout\[0\]~reg0 cin clk 3.651 ns register " "Info: tsu for register \"qout\[0\]~reg0\" (data pin = \"cin\", clock pin = \"clk\") is 3.651 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.513 ns + Longest pin register " "Info: + Longest pin to register delay is 6.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns cin 1 PIN PIN_A7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_A7; Fanout = 2; PIN Node = 'cin'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.879 ns) + CELL(0.366 ns) 5.332 ns qout\[2\]~615 2 COMB LC_X41_Y30_N2 4 " "Info: 2: + IC(3.879 ns) + CELL(0.366 ns) = 5.332 ns; Loc. = LC_X41_Y30_N2; Fanout = 4; COMB Node = 'qout\[2\]~615'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.245 ns" { cin qout[2]~615 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.476 ns) + CELL(0.705 ns) 6.513 ns qout\[0\]~reg0 3 REG LC_X41_Y30_N4 6 " "Info: 3: + IC(0.476 ns) + CELL(0.705 ns) = 6.513 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.181 ns" { qout[2]~615 qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 33.13 % ) " "Info: Total cell delay = 2.158 ns ( 33.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.355 ns ( 66.87 % ) " "Info: Total interconnect delay = 4.355 ns ( 66.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.513 ns" { cin qout[2]~615 qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "6.513 ns" { cin cin~out0 qout[2]~615 qout[0]~reg0 } { 0.000ns 0.000ns 3.879ns 0.476ns } { 0.000ns 1.087ns 0.366ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.872 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns qout\[0\]~reg0 2 REG LC_X41_Y30_N4 6 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.044 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.513 ns" { cin qout[2]~615 qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "6.513 ns" { cin cin~out0 qout[2]~615 qout[0]~reg0 } { 0.000ns 0.000ns 3.879ns 0.476ns } { 0.000ns 1.087ns 0.366ns 0.705ns } } } { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk cout qout\[0\]~reg0 8.052 ns register " "Info: tco from clock \"clk\" to destination pin \"cout\" through register \"qout\[0\]~reg0\" is 8.052 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.872 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.502 ns) + CELL(0.542 ns) 2.872 ns qout\[0\]~reg0 2 REG LC_X41_Y30_N4 6 " "Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.044 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.70 % ) " "Info: Total cell delay = 1.370 ns ( 47.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.502 ns ( 52.30 % ) " "Info: Total interconnect delay = 1.502 ns ( 52.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.024 ns + Longest register pin " "Info: + Longest register to pin delay is 5.024 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qout\[0\]~reg0 1 REG LC_X41_Y30_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout\[0\]~reg0'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { qout[0]~reg0 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.432 ns) + CELL(0.366 ns) 0.798 ns cout~27 2 COMB LC_X41_Y30_N7 3 " "Info: 2: + IC(0.432 ns) + CELL(0.366 ns) = 0.798 ns; Loc. = LC_X41_Y30_N7; Fanout = 3; COMB Node = 'cout~27'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.798 ns" { qout[0]~reg0 cout~27 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.183 ns) 1.481 ns cout~28 3 COMB LC_X41_Y30_N3 2 " "Info: 3: + IC(0.500 ns) + CELL(0.183 ns) = 1.481 ns; Loc. = LC_X41_Y30_N3; Fanout = 2; COMB Node = 'cout~28'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.683 ns" { cout~27 cout~28 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(2.404 ns) 5.024 ns cout 4 PIN PIN_G8 0 " "Info: 4: + IC(1.139 ns) + CELL(2.404 ns) = 5.024 ns; Loc. = PIN_G8; Fanout = 0; PIN Node = 'cout'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.543 ns" { cout~28 cout } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.953 ns ( 58.78 % ) " "Info: Total cell delay = 2.953 ns ( 58.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.071 ns ( 41.22 % ) " "Info: Total interconnect delay = 2.071 ns ( 41.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.024 ns" { qout[0]~reg0 cout~27 cout~28 cout } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "5.024 ns" { qout[0]~reg0 cout~27 cout~28 cout } { 0.000ns 0.432ns 0.500ns 1.139ns } { 0.000ns 0.366ns 0.183ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.872 ns" { clk qout[0]~reg0 } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "2.872 ns" { clk clk~out0 qout[0]~reg0 } { 0.000ns 0.000ns 1.502ns } { 0.000ns 0.828ns 0.542ns } } } { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.024 ns" { qout[0]~reg0 cout~27 cout~28 cout } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "5.024 ns" { qout[0]~reg0 cout~27 cout~28 cout } { 0.000ns 0.432ns 0.500ns 1.139ns } { 0.000ns 0.366ns 0.183ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "cin cout 8.570 ns Longest " "Info: Longest tpd from source pin \"cin\" to destination pin \"cout\" is 8.570 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns cin 1 PIN PIN_A7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_A7; Fanout = 2; PIN Node = 'cin'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { cin } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.865 ns) + CELL(0.075 ns) 5.027 ns cout~28 2 COMB LC_X41_Y30_N3 2 " "Info: 2: + IC(3.865 ns) + CELL(0.075 ns) = 5.027 ns; Loc. = LC_X41_Y30_N3; Fanout = 2; COMB Node = 'cout~28'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.940 ns" { cin cout~28 } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(2.404 ns) 8.570 ns cout 3 PIN PIN_G8 0 " "Info: 3: + IC(1.139 ns) + CELL(2.404 ns) = 8.570 ns; Loc. = PIN_G8; Fanout = 0; PIN Node = 'cout'" {  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.543 ns" { cout~28 cout } "NODE_NAME" } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.566 ns ( 41.61 % ) " "Info: Total cell delay = 3.566 ns ( 41.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.004 ns ( 58.39 % ) " "Info: Total interconnect delay = 5.004 ns ( 58.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus6.0/win/TimingClosureFloorplan.fld" "" "8.570 ns" { cin cout~28 cout } "NODE_NAME" } } { "e:/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus6.0/win/Technology_Viewer.qrui" "8.570 ns" { cin cin~out0 cout~28 cout } { 0.000ns 0.000ns 3.865ns 1.139ns } { 0.000ns 1.087ns 0.075ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}