count__10.hier_info

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

|count__10
cin => qout~4.OUTPUTSELECT
cin => qout~5.OUTPUTSELECT
cin => qout~6.OUTPUTSELECT
cin => qout~7.OUTPUTSELECT
cin => cout~0.IN1
clk => qout[2]~reg0.CLK
clk => qout[1]~reg0.CLK
clk => qout[0]~reg0.CLK
clk => qout[3]~reg0.CLK
 renamed_port_1 <= cout~0.DB_MAX_OUTPUT_PORT_TYPE
qout[0] <= qout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[1] <= qout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[2] <= qout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
qout[3] <= qout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cout <= cout~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => qout~11.DATAB
data[1] => qout~10.DATAB
data[2] => qout~9.DATAB
data[3] => qout~8.DATAB
load => qout~8.OUTPUTSELECT
load => qout~9.OUTPUTSELECT
load => qout~10.OUTPUTSELECT
load => qout~11.OUTPUTSELECT
reset => qout[2]~reg0.ACLR
reset => qout[1]~reg0.ACLR
reset => qout[0]~reg0.ACLR
reset => qout[3]~reg0.ACLR