count__10.fnsim.qmsg

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 29 12:20:21 2009 " "Info: Processing started: Sun Mar 29 12:20:21 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off count__10 -c count__10 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off count__10 -c count__10 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count__10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file count__10.v" { { "Info" "ISGN_ENTITY_NAME" "1 count__10 " "Info: Found entity 1: count__10" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "count__10 " "Info: Elaborating entity \"count__10\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 count__10.v(16) " "Warning (10230): Verilog HDL assignment warning at count__10.v(16): truncated value with size 32 to match size of target (4)" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 count__10.v(19) " "Warning (10230): Verilog HDL assignment warning at count__10.v(19): truncated value with size 32 to match size of target (1)" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_PORT_IS_ALREADY_DEFINED_WARNING" "cout count__10.v(1) " "Warning (10136): Verilog HDL Module Declaration warning at count__10.v(1): port \"cout\" already exists in the list of ports" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 1 0 0 } }  } 0 10136 "Verilog HDL Module Declaration warning at %2!s!: port \"%1!s!\" already exists in the list of ports" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartus6.0/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "count__10.v" "" { Text "E:/quartus6.0/my_desgin/count__10/count__10.v" 16 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 3 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 12:20:21 2009 " "Info: Processing ended: Sun Mar 29 12:20:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}