count__10.map.summary

来自「这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sun Mar 29 12:18:36 2009
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : count__10
Top-level Entity Name : count__10
Family : Stratix
Total logic elements : 10
Total pins : 14
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0