count__10.tan.rpt

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

+-------+--------------+------------+--------------+-----------------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To              ; From Clock ;
+-------+--------------+------------+--------------+-----------------+------------+
; N/A   ; None         ; 8.052 ns   ; qout[0]~reg0 ; cout            ; clk        ;
; N/A   ; None         ; 8.052 ns   ; qout[0]~reg0 ;  renamed_port_1 ; clk        ;
; N/A   ; None         ; 7.937 ns   ; qout[1]~reg0 ; cout            ; clk        ;
; N/A   ; None         ; 7.937 ns   ; qout[1]~reg0 ;  renamed_port_1 ; clk        ;
; N/A   ; None         ; 7.850 ns   ; qout[3]~reg0 ; cout            ; clk        ;
; N/A   ; None         ; 7.850 ns   ; qout[3]~reg0 ;  renamed_port_1 ; clk        ;
; N/A   ; None         ; 7.743 ns   ; qout[2]~reg0 ; cout            ; clk        ;
; N/A   ; None         ; 7.743 ns   ; qout[2]~reg0 ;  renamed_port_1 ; clk        ;
; N/A   ; None         ; 7.669 ns   ; qout[2]~reg0 ; qout[2]         ; clk        ;
; N/A   ; None         ; 6.879 ns   ; qout[0]~reg0 ; qout[0]         ; clk        ;
; N/A   ; None         ; 6.822 ns   ; qout[3]~reg0 ; qout[3]         ; clk        ;
; N/A   ; None         ; 6.598 ns   ; qout[1]~reg0 ; qout[1]         ; clk        ;
+-------+--------------+------------+--------------+-----------------+------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+------+-----------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To              ;
+-------+-------------------+-----------------+------+-----------------+
; N/A   ; None              ; 8.570 ns        ; cin  ; cout            ;
; N/A   ; None              ; 8.570 ns        ; cin  ;  renamed_port_1 ;
+-------+-------------------+-----------------+------+-----------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+---------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To           ; To Clock ;
+---------------+-------------+-----------+---------+--------------+----------+
; N/A           ; None        ; -2.350 ns ; data[0] ; qout[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.369 ns ; data[3] ; qout[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.400 ns ; load    ; qout[3]~reg0 ; clk      ;
; N/A           ; None        ; -2.407 ns ; load    ; qout[0]~reg0 ; clk      ;
; N/A           ; None        ; -2.409 ns ; load    ; qout[1]~reg0 ; clk      ;
; N/A           ; None        ; -2.411 ns ; load    ; qout[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.502 ns ; data[2] ; qout[2]~reg0 ; clk      ;
; N/A           ; None        ; -2.694 ns ; data[1] ; qout[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.541 ns ; cin     ; qout[0]~reg0 ; clk      ;
; N/A           ; None        ; -3.541 ns ; cin     ; qout[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.541 ns ; cin     ; qout[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.541 ns ; cin     ; qout[1]~reg0 ; clk      ;
+---------------+-------------+-----------+---------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Mar 29 12:18:47 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off count__10 -c count__10 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "qout[0]~reg0" and destination register "qout[3]~reg0"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.454 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
            Info: 2: + IC(0.432 ns) + CELL(0.366 ns) = 0.798 ns; Loc. = LC_X41_Y30_N7; Fanout = 3; COMB Node = 'cout~27'
            Info: 3: + IC(0.337 ns) + CELL(0.319 ns) = 1.454 ns; Loc. = LC_X41_Y30_N1; Fanout = 3; REG Node = 'qout[3]~reg0'
            Info: Total cell delay = 0.685 ns ( 47.11 % )
            Info: Total interconnect delay = 0.769 ns ( 52.89 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.872 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N1; Fanout = 3; REG Node = 'qout[3]~reg0'
                Info: Total cell delay = 1.370 ns ( 47.70 % )
                Info: Total interconnect delay = 1.502 ns ( 52.30 % )
            Info: - Longest clock path from clock "clk" to source register is 2.872 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
                Info: Total cell delay = 1.370 ns ( 47.70 % )
                Info: Total interconnect delay = 1.502 ns ( 52.30 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "qout[0]~reg0" (data pin = "cin", clock pin = "clk") is 3.651 ns
    Info: + Longest pin to register delay is 6.513 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_A7; Fanout = 2; PIN Node = 'cin'
        Info: 2: + IC(3.879 ns) + CELL(0.366 ns) = 5.332 ns; Loc. = LC_X41_Y30_N2; Fanout = 4; COMB Node = 'qout[2]~615'
        Info: 3: + IC(0.476 ns) + CELL(0.705 ns) = 6.513 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
        Info: Total cell delay = 2.158 ns ( 33.13 % )
        Info: Total interconnect delay = 4.355 ns ( 66.87 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.872 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
        Info: Total cell delay = 1.370 ns ( 47.70 % )
        Info: Total interconnect delay = 1.502 ns ( 52.30 % )
Info: tco from clock "clk" to destination pin "cout" through register "qout[0]~reg0" is 8.052 ns
    Info: + Longest clock path from clock "clk" to source register is 2.872 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
        Info: Total cell delay = 1.370 ns ( 47.70 % )
        Info: Total interconnect delay = 1.502 ns ( 52.30 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.024 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
        Info: 2: + IC(0.432 ns) + CELL(0.366 ns) = 0.798 ns; Loc. = LC_X41_Y30_N7; Fanout = 3; COMB Node = 'cout~27'
        Info: 3: + IC(0.500 ns) + CELL(0.183 ns) = 1.481 ns; Loc. = LC_X41_Y30_N3; Fanout = 2; COMB Node = 'cout~28'
        Info: 4: + IC(1.139 ns) + CELL(2.404 ns) = 5.024 ns; Loc. = PIN_G8; Fanout = 0; PIN Node = 'cout'
        Info: Total cell delay = 2.953 ns ( 58.78 % )
        Info: Total interconnect delay = 2.071 ns ( 41.22 % )
Info: Longest tpd from source pin "cin" to destination pin "cout" is 8.570 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_A7; Fanout = 2; PIN Node = 'cin'
    Info: 2: + IC(3.865 ns) + CELL(0.075 ns) = 5.027 ns; Loc. = LC_X41_Y30_N3; Fanout = 2; COMB Node = 'cout~28'
    Info: 3: + IC(1.139 ns) + CELL(2.404 ns) = 8.570 ns; Loc. = PIN_G8; Fanout = 0; PIN Node = 'cout'
    Info: Total cell delay = 3.566 ns ( 41.61 % )
    Info: Total interconnect delay = 5.004 ns ( 58.39 % )
Info: th for register "qout[0]~reg0" (data pin = "data[0]", clock pin = "clk") is -2.350 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.872 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.502 ns) + CELL(0.542 ns) = 2.872 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
        Info: Total cell delay = 1.370 ns ( 47.70 % )
        Info: Total interconnect delay = 1.502 ns ( 52.30 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.322 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_H8; Fanout = 1; PIN Node = 'data[0]'
        Info: 2: + IC(3.696 ns) + CELL(0.539 ns) = 5.322 ns; Loc. = LC_X41_Y30_N4; Fanout = 6; REG Node = 'qout[0]~reg0'
        Info: Total cell delay = 1.626 ns ( 30.55 % )
        Info: Total interconnect delay = 3.696 ns ( 69.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 29 12:18:48 2009
    Info: Elapsed time: 00:00:01