📄 count__10.tan.rpt
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Timing Analyzer report for count__10
Sun Mar 29 12:18:48 2009
Version 6.0 Build 178 04/27/2006 SJ Web Edition
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+-----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+-----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.651 ns ; cin ; qout[1]~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 8.052 ns ; qout[0]~reg0 ; renamed_port_1 ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 8.570 ns ; cin ; renamed_port_1 ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.350 ns ; data[0] ; qout[0]~reg0 ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[0]~reg0 ; qout[3]~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+-----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[0]~reg0 ; qout[3]~reg0 ; clk ; clk ; None ; None ; 1.454 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[0]~reg0 ; qout[1]~reg0 ; clk ; clk ; None ; None ; 1.452 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[1]~reg0 ; qout[3]~reg0 ; clk ; clk ; None ; None ; 1.339 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[1]~reg0 ; qout[1]~reg0 ; clk ; clk ; None ; None ; 1.337 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[3]~reg0 ; qout[3]~reg0 ; clk ; clk ; None ; None ; 1.252 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[3]~reg0 ; qout[1]~reg0 ; clk ; clk ; None ; None ; 1.250 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[2]~reg0 ; qout[3]~reg0 ; clk ; clk ; None ; None ; 1.145 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[2]~reg0 ; qout[1]~reg0 ; clk ; clk ; None ; None ; 1.143 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[2]~reg0 ; qout[2]~reg0 ; clk ; clk ; None ; None ; 1.140 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[1]~reg0 ; qout[2]~reg0 ; clk ; clk ; None ; None ; 1.042 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[0]~reg0 ; qout[0]~reg0 ; clk ; clk ; None ; None ; 0.873 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; qout[0]~reg0 ; qout[2]~reg0 ; clk ; clk ; None ; None ; 0.852 ns ;
+-------+------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+---------+--------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+---------+--------------+----------+
; N/A ; None ; 3.651 ns ; cin ; qout[0]~reg0 ; clk ;
; N/A ; None ; 3.651 ns ; cin ; qout[3]~reg0 ; clk ;
; N/A ; None ; 3.651 ns ; cin ; qout[2]~reg0 ; clk ;
; N/A ; None ; 3.651 ns ; cin ; qout[1]~reg0 ; clk ;
; N/A ; None ; 3.317 ns ; load ; qout[0]~reg0 ; clk ;
; N/A ; None ; 3.317 ns ; load ; qout[3]~reg0 ; clk ;
; N/A ; None ; 3.317 ns ; load ; qout[2]~reg0 ; clk ;
; N/A ; None ; 3.317 ns ; load ; qout[1]~reg0 ; clk ;
; N/A ; None ; 2.804 ns ; data[1] ; qout[1]~reg0 ; clk ;
; N/A ; None ; 2.612 ns ; data[2] ; qout[2]~reg0 ; clk ;
; N/A ; None ; 2.479 ns ; data[3] ; qout[3]~reg0 ; clk ;
; N/A ; None ; 2.460 ns ; data[0] ; qout[0]~reg0 ; clk ;
+-------+--------------+------------+---------+--------------+----------+
+---------------------------------------------------------------------------------+
; tco ;
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