count__10.tan.summary

这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.651 ns
From           : cin
To             : qout[1]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.052 ns
From           : qout[0]~reg0
To             :  renamed_port_1
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.570 ns
From           : cin
To             :  renamed_port_1
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.350 ns
From           : data[0]
To             : qout[0]~reg0
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 422.12 MHz ( period = 2.369 ns )
From           : qout[0]~reg0
To             : qout[3]~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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