async_fifo_tb.v

fifo pointers in verilog gray code utilization for synchronius

`timescale 1ps/1ps
module async_fifo_tb ();

`include "async_fifo_defines.v"

parameter wclk_period = 24;
parameter rclk_period = 3200;
parameter wrst_n_period = 10;
parameter rrst_n_period = 20;


parameter TB_DELAY = 20;

reg wclk;
reg rclk;
reg wrst_n;
reg rrst_n;

reg end_of_sim;

integer wclk_period_rand;
integer rclk_period_rand;

wire rinc_tb_wire;
wire [`DSIZE-1:0] rdata_tb_wire;
wire rempty_tb_wire;
wire winc_tb_wire;
wire wfull_tb_wire;
wire [`DSIZE-1:0] wdata_tb_wire;

event change_clk_period;

fifo2
                #(
                  .DSIZE(`DSIZE),
                  .ASIZE(`ASIZE)
                 )
             async_fifo_U (
                .rdata(rdata_tb_wire),
                .wfull(wfull_tb_wire),
                .rempty(rempty_tb_wire),
                .wdata(wdata_tb_wire),

                .winc(winc_tb_wire),
                .wclk(wclk),
                .wrst_n(wrst_n),
                .rinc(rinc_tb_wire),
                .rclk(rclk),
`ifdef OPT_PTR
                .threshhold(async_fifo_inf_U.threshhold),
`endif
                .rrst_n(rrst_n)
                );

async_fifo_if
                #(
                  .DSIZE(`DSIZE),
                  .ASIZE(`ASIZE)
                 )
             async_fifo_inf_U(
                .wclk(wclk),
                .rclk(rclk),
                .wrst_n(wrst_n),
                .rrst_n(rrst_n)
                );

assign #TB_DELAY async_fifo_inf_U.end_of_sim = end_of_sim;
assign #TB_DELAY async_fifo_inf_U.wclk_period_rand = wclk_period_rand;
assign #TB_DELAY async_fifo_inf_U.rclk_period_rand = rclk_period_rand;
assign #TB_DELAY rinc_tb_wire = async_fifo_inf_U.rinc;
assign #TB_DELAY async_fifo_inf_U.rinc_tb_wire = async_fifo_inf_U.rinc;
assign #TB_DELAY async_fifo_inf_U.rdata = rdata_tb_wire;
assign #TB_DELAY async_fifo_inf_U.rempty = rempty_tb_wire;
assign #TB_DELAY winc_tb_wire = async_fifo_inf_U.winc;
assign #TB_DELAY async_fifo_inf_U.winc_tb_wire = async_fifo_inf_U.winc;
assign #TB_DELAY async_fifo_inf_U.wfull = wfull_tb_wire;
assign #TB_DELAY wdata_tb_wire = async_fifo_inf_U.wdata;
assign #TB_DELAY async_fifo_inf_U.wdata_tb_wire = async_fifo_inf_U.wdata;


async_fifo_tb_program
                #(
                  .wclk_period(wclk_period),
                  .rclk_period(rclk_period),
                  .DSIZE(`DSIZE),
                  .ASIZE(`ASIZE)
                 )
             async_fifo_tb_program_U (
                .async_fifo_inf(async_fifo_inf_U)
                );


initial
begin
    wclk <= 1'b0;
    rclk <= 1'b0;
    wrst_n <= 1'b0;
    rrst_n <= 1'b0;
end


initial
begin
    forever
    begin
  //`ifdef FIFO_GLS_SDF
  //    wclk_period_rand = $urandom_range(3000,20);
  //`else
  //    wclk_period_rand = $urandom_range(3000,20);
  //`endif
      //wclk_period_rand = wclk_period;
      wclk <= 1'b0;
      #(wclk_period_rand/2);
      wclk <= 1'b1;
      #(wclk_period_rand/2);
    end
end

initial
begin
    forever
    begin
       wclk_period_rand = $urandom_range(2,2_000);
       rclk_period_rand = $urandom_range(900_000,2_000);
       //rclk_period_rand = 100_000;
       //wclk_period_rand = 2_000;
       $display("WRITE TO READ RATIO is %d", (rclk_period_rand/wclk_period_rand ==0) ? wclk_period_rand/rclk_period_rand : rclk_period_rand/wclk_period_rand);
       @ (change_clk_period);
    end
end

initial
begin
    forever
    begin
  //`ifdef FIFO_GLS_SDF
  //    rclk_period_rand = $urandom_range(3000,20);
  //`else
  //    rclk_period_rand = $urandom_range(3000,20);
  //`endif
      //rclk_period_rand = rclk_period;
      rclk <= 1'b0;
      #(rclk_period_rand/2);
      rclk <= 1'b1;
      #(rclk_period_rand/2);
    end
end


initial
begin
   forever
   begin
      ->change_clk_period;
      #900_0000;
   end
end

initial
begin
    repeat (wrst_n_period) @( posedge wclk);
    wrst_n <= 1'b1;
end



initial
begin
    repeat (rrst_n_period) @( posedge rclk);
    rrst_n <= 1'b1;
end


initial
begin
   $vcdpluson();
   $vcdplusmemon();
`ifdef _NCVERILOG
   $shm_open(waves_shm);
   $shm_probe("AC", async_fifo_tb);
   //$shm_probe("AC", async_fifo_tb_U);
`endif
end


initial
begin
  end_of_sim = 1'b0;
  repeat (9000000) @(posedge rclk);
  end_of_sim = 1'b1;
  #20;
  $display("TEST PASSED");
  $finish;
end

initial
begin
  `ifdef FIFO_GLS_SDF
      $sdf_annotate("./netlist/fifo2.sdf", async_fifo_U);
  `endif
end


endmodule