cnt12_24.vhd

来自「用VHDL实现的完整数字钟代码」· VHDL 代码 · 共 57 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT12_24 IS
PORT(CLK,RST,EN,set1224:IN STD_LOGIC;
        COUT1:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        COUT2:  OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
           CO:  OUT STD_LOGIC);
END  ;
 
ARCHITECTURE one OF  CNT12_24 IS
BEGIN
PROCESS(CLK,RST,EN,set1224)
VARIABLE CQI1:  STD_LOGIC_VECTOR(3 DOWNTO 0);
 VARIABLE  CQI2: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF RST='1' THEN CQI1:=(OTHERS=>'0');  CQI2:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
   IF EN='1' THEN
      if set1224='1'then  
         IF CQI1=3 THEN
           IF CQI2=2 THEN   
           CQI1:=(OTHERS=>'0');
           CQI2:=(OTHERS=>'0');
           ELSE CQI1:=CQI1+1;
           END IF;
           ELSIF  CQI1=9 THEN
          CQI1:=(OTHERS=>'0');
          CQI2:=CQI2+1;
         ELSe CQI1:=CQI1+1;
        END IF; 
      elsif   set1224='0' then 
        if cqi1=0 then CQI1:="0001";
        elsIF CQI1=2 THEN
           IF CQI2=1 THEN   
           CQI1:="0001";
           CQI2:=(OTHERS=>'0');
           ELSE CQI1:=CQI1+1;
           END IF;
        ELSIF  CQI1=9 THEN
          CQI1:=(OTHERS=>'0');
          CQI2:=CQI2+1;
       ELSe CQI1:=CQI1+1;
        END IF; 
      END IF;
    END IF;
 END IF;
 IF CQI1=3 AND CQI2=2 THEN CO<='1';
  ELSif CQI1=2 AND CQI2=1 THEN CO<='1';

    else CO<='0';
 END IF;
COUT1<=CQI1;
COUT2<=CQI2;
END PROCeSS;
END ;