led.vhd

用VHDL实现的完整数字钟代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY LED IS
 PORT(ADIN :IN STD_LOGIC_VECTOR(23 DOWNTO 0);
      CK:IN STD_LOGIC;
SEG :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END LED;
ARCHITECTURE one OF LED IS
SIGNAL NUM:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(CK)
BEGIN
IF CK'EVENT AND CK='1' THEN 
   IF COUNT<5 THEN COUNT<=COUNT+1;
   ELSE COUNT<=(OTHERS=>'0');
   END IF;
END IF;
END PROCESS;
SEL<=COUNT;
NUM<=ADIN(3 DOWNTO 0)WHEN COUNT=0 ELSE
     ADIN(7 DOWNTO 4)WHEN COUNT=1 ELSE
     ADIN(11 DOWNTO 8)WHEN COUNT=2 ELSE
     ADIN(15 DOWNTO 12)WHEN COUNT=3 ELSE
     ADIN(19 DOWNTO 16)WHEN COUNT=4 ELSE
     ADIN(23 DOWNTO 20);
SEG<="0111111" WHEN NUM=0 ELSE
"0000110" WHEN NUM=1 ELSE
"1011011" WHEN NUM=2 ELSE
"1001111" WHEN NUM=3 ELSE
"1100110" WHEN NUM=4 ELSE
"1101101" WHEN NUM=5 ELSE
"1111101" WHEN NUM=6 ELSE
"0000111" WHEN NUM=7 ELSE
"1111111" WHEN NUM=8 ELSE
"1101111";
END ;