clock.hier_info

用VHDL实现的完整数字钟代码

|clock
CLK1 => CNT60:U4.CLK
CLK1024 => FM:U6.CLK1024
CLK1024 => led:U5.CK
CLK2048 => FM:U6.CLK2048
SELJ => CONTROL:U1.JS
STEH => CONTROL:U1.CLKH
SETM => CONTROL:U1.CLKM
RST => CNT60:U4.RST
RST => CNT60:U3.RST
RST => CNT12_24:U2.RST
S1224 => CNT12_24:U2.set1224
SEGd[0] <= led:U5.SEG[0]
SEGd[1] <= led:U5.SEG[1]
SEGd[2] <= led:U5.SEG[2]
SEGd[3] <= led:U5.SEG[3]
SEGd[4] <= led:U5.SEG[4]
SEGd[5] <= led:U5.SEG[5]
SEGd[6] <= led:U5.SEG[6]
SELd[0] <= led:U5.SEL[0]
SELd[1] <= led:U5.SEL[1]
SELd[2] <= led:U5.SEL[2]
FeM <= FM:U6.QFM


|clock|CONTROL:U1
CLKH => CPH~0.DATAA
CLKM => CPM~0.DATAA
JS => CPM~0.OUTPUTSELECT
JS => CPH~0.OUTPUTSELECT
QS => CPM~0.DATAB
QM => CPH~0.DATAB
ENH <= <VCC>
ENM <= <VCC>
CPH <= CPH~0.DB_MAX_OUTPUT_PORT_TYPE
CPM <= CPM~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|CNT12_24:U2
CLK => CQI1[3].CLK
CLK => CQI1[2].CLK
CLK => CQI1[1].CLK
CLK => CQI1[0].CLK
CLK => CQI2[3].CLK
CLK => CQI2[2].CLK
CLK => CQI2[1].CLK
CLK => CQI2[0].CLK
RST => CQI1[3].ACLR
RST => CQI1[2].ACLR
RST => CQI1[1].ACLR
RST => CQI1[0].ACLR
RST => CQI2[3].ACLR
RST => CQI2[2].ACLR
RST => CQI2[1].ACLR
RST => CQI2[0].ACLR
EN => CQI1[3].ENA
EN => CQI1[2].ENA
EN => CQI1[1].ENA
EN => CQI2[0].ENA
EN => CQI1[0].ENA
EN => CQI2[3].ENA
EN => CQI2[2].ENA
EN => CQI2[1].ENA
set1224 => CQI2~27.OUTPUTSELECT
set1224 => CQI2~26.OUTPUTSELECT
set1224 => CQI2~25.OUTPUTSELECT
set1224 => CQI2~24.OUTPUTSELECT
set1224 => CQI1~0.OUTPUTSELECT
set1224 => CQI1~9.OUTPUTSELECT
set1224 => CQI1~26.OUTPUTSELECT
set1224 => CQI1~27.OUTPUTSELECT
COUT1[0] <= CQI1[0].DB_MAX_OUTPUT_PORT_TYPE
COUT1[1] <= CQI1[1].DB_MAX_OUTPUT_PORT_TYPE
COUT1[2] <= CQI1[2].DB_MAX_OUTPUT_PORT_TYPE
COUT1[3] <= CQI1[3].DB_MAX_OUTPUT_PORT_TYPE
COUT2[0] <= CQI2[0].DB_MAX_OUTPUT_PORT_TYPE
COUT2[1] <= CQI2[1].DB_MAX_OUTPUT_PORT_TYPE
COUT2[2] <= CQI2[2].DB_MAX_OUTPUT_PORT_TYPE
COUT2[3] <= CQI2[3].DB_MAX_OUTPUT_PORT_TYPE
CO <= CO~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|CNT60:U3
CLK => CQI1[3].CLK
CLK => CQI1[2].CLK
CLK => CQI1[1].CLK
CLK => CQI1[0].CLK
CLK => CQI2[3].CLK
CLK => CQI2[2].CLK
CLK => CQI2[1].CLK
CLK => CQI2[0].CLK
RST => CQI1[3].ACLR
RST => CQI1[2].ACLR
RST => CQI1[1].ACLR
RST => CQI1[0].ACLR
RST => CQI2[3].ACLR
RST => CQI2[2].ACLR
RST => CQI2[1].ACLR
RST => CQI2[0].ACLR
EN => CQI1[3].ENA
EN => CQI1[2].ENA
EN => CQI1[1].ENA
EN => CQI1[0].ENA
EN => CQI2[3].ENA
EN => CQI2[2].ENA
EN => CQI2[1].ENA
EN => CQI2[0].ENA
COUT1[0] <= CQI1[0].DB_MAX_OUTPUT_PORT_TYPE
COUT1[1] <= CQI1[1].DB_MAX_OUTPUT_PORT_TYPE
COUT1[2] <= CQI1[2].DB_MAX_OUTPUT_PORT_TYPE
COUT1[3] <= CQI1[3].DB_MAX_OUTPUT_PORT_TYPE
COUT2[0] <= CQI2[0].DB_MAX_OUTPUT_PORT_TYPE
COUT2[1] <= CQI2[1].DB_MAX_OUTPUT_PORT_TYPE
COUT2[2] <= CQI2[2].DB_MAX_OUTPUT_PORT_TYPE
COUT2[3] <= CQI2[3].DB_MAX_OUTPUT_PORT_TYPE
CO <= process0~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|CNT60:U4
CLK => CQI1[3].CLK
CLK => CQI1[2].CLK
CLK => CQI1[1].CLK
CLK => CQI1[0].CLK
CLK => CQI2[3].CLK
CLK => CQI2[2].CLK
CLK => CQI2[1].CLK
CLK => CQI2[0].CLK
RST => CQI1[3].ACLR
RST => CQI1[2].ACLR
RST => CQI1[1].ACLR
RST => CQI1[0].ACLR
RST => CQI2[3].ACLR
RST => CQI2[2].ACLR
RST => CQI2[1].ACLR
RST => CQI2[0].ACLR
EN => CQI1[3].ENA
EN => CQI1[2].ENA
EN => CQI1[1].ENA
EN => CQI1[0].ENA
EN => CQI2[3].ENA
EN => CQI2[2].ENA
EN => CQI2[1].ENA
EN => CQI2[0].ENA
COUT1[0] <= CQI1[0].DB_MAX_OUTPUT_PORT_TYPE
COUT1[1] <= CQI1[1].DB_MAX_OUTPUT_PORT_TYPE
COUT1[2] <= CQI1[2].DB_MAX_OUTPUT_PORT_TYPE
COUT1[3] <= CQI1[3].DB_MAX_OUTPUT_PORT_TYPE
COUT2[0] <= CQI2[0].DB_MAX_OUTPUT_PORT_TYPE
COUT2[1] <= CQI2[1].DB_MAX_OUTPUT_PORT_TYPE
COUT2[2] <= CQI2[2].DB_MAX_OUTPUT_PORT_TYPE
COUT2[3] <= CQI2[3].DB_MAX_OUTPUT_PORT_TYPE
CO <= process0~0.DB_MAX_OUTPUT_PORT_TYPE


|clock|LED:U5
ADIN[0] => NUM[0].DATAB
ADIN[1] => NUM[1].DATAB
ADIN[2] => NUM[2].DATAB
ADIN[3] => NUM[3].DATAB
ADIN[4] => NUM~15.DATAB
ADIN[5] => NUM~14.DATAB
ADIN[6] => NUM~13.DATAB
ADIN[7] => NUM~12.DATAB
ADIN[8] => NUM~11.DATAB
ADIN[9] => NUM~10.DATAB
ADIN[10] => NUM~9.DATAB
ADIN[11] => NUM~8.DATAB
ADIN[12] => NUM~7.DATAB
ADIN[13] => NUM~6.DATAB
ADIN[14] => NUM~5.DATAB
ADIN[15] => NUM~4.DATAB
ADIN[16] => NUM~3.DATAB
ADIN[17] => NUM~2.DATAB
ADIN[18] => NUM~1.DATAB
ADIN[19] => NUM~0.DATAB
ADIN[20] => NUM~3.DATAA
ADIN[21] => NUM~2.DATAA
ADIN[22] => NUM~1.DATAA
ADIN[23] => NUM~0.DATAA
CK => COUNT[2].CLK
CK => COUNT[1].CLK
CK => COUNT[0].CLK
SEG[0] <= SEG~35.DB_MAX_OUTPUT_PORT_TYPE
SEG[1] <= SEG~34.DB_MAX_OUTPUT_PORT_TYPE
SEG[2] <= SEG~33.DB_MAX_OUTPUT_PORT_TYPE
SEG[3] <= SEG~32.DB_MAX_OUTPUT_PORT_TYPE
SEG[4] <= SEG~31.DB_MAX_OUTPUT_PORT_TYPE
SEG[5] <= SEG~30.DB_MAX_OUTPUT_PORT_TYPE
SEG[6] <= SEG~29.DB_MAX_OUTPUT_PORT_TYPE
SEL[0] <= COUNT[0].DB_MAX_OUTPUT_PORT_TYPE
SEL[1] <= COUNT[1].DB_MAX_OUTPUT_PORT_TYPE
SEL[2] <= COUNT[2].DB_MAX_OUTPUT_PORT_TYPE


|clock|FM:U6
CLK1024 => QFM~1.DATAB
CLK2048 => QFM~1.DATAA
FS10[0] => Equal2.IN9
FS10[1] => Equal2.IN8
FS10[2] => Equal2.IN7
FS10[3] => Equal2.IN6
FS1[0] => Equal7.IN9
FS1[0] => Equal6.IN9
FS1[0] => Equal5.IN9
FS1[0] => Equal4.IN9
FS1[0] => Equal3.IN9
FS1[1] => Equal7.IN8
FS1[1] => Equal6.IN8
FS1[1] => Equal5.IN8
FS1[1] => Equal4.IN8
FS1[1] => Equal3.IN8
FS1[2] => Equal7.IN7
FS1[2] => Equal6.IN7
FS1[2] => Equal5.IN7
FS1[2] => Equal4.IN7
FS1[2] => Equal3.IN7
FS1[3] => Equal7.IN6
FS1[3] => Equal6.IN6
FS1[3] => Equal5.IN6
FS1[3] => Equal4.IN6
FS1[3] => Equal3.IN6
FM10[0] => Equal0.IN9
FM10[1] => Equal0.IN8
FM10[2] => Equal0.IN7
FM10[3] => Equal0.IN6
FM1[0] => Equal1.IN9
FM1[1] => Equal1.IN8
FM1[2] => Equal1.IN7
FM1[3] => Equal1.IN6
QFM <= QFM$latch.DB_MAX_OUTPUT_PORT_TYPE