clock.map.qmsg

用VHDL实现的完整数字钟代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 04 16:54:34 2008 " "Info: Processing started: Thu Dec 04 16:54:34 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-one " "Info: Found design unit 1: clock-one" {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt12_24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt12_24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT12_24-one " "Info: Found design unit 1: CNT12_24-one" {  } { { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT12_24 " "Info: Found entity 1: CNT12_24" {  } { { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT60-one " "Info: Found design unit 1: CNT60-one" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT60 " "Info: Found entity 1: CNT60" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CONTROL-one " "Info: Found design unit 1: CONTROL-one" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CONTROL " "Info: Found entity 1: CONTROL" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file timer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FM-one " "Info: Found design unit 1: FM-one" {  } { { "timer.vhd" "" { Text "E:/EDA2006073071/clock/timer.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FM " "Info: Found entity 1: FM" {  } { { "timer.vhd" "" { Text "E:/EDA2006073071/clock/timer.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LED-one " "Info: Found design unit 1: LED-one" {  } { { "led.vhd" "" { Text "E:/EDA2006073071/clock/led.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 LED " "Info: Found entity 1: LED" {  } { { "led.vhd" "" { Text "E:/EDA2006073071/clock/led.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "MFS clock.vhd(49) " "Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal \"MFS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 49 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "MFG clock.vhd(49) " "Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal \"MFG\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 49 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SFS clock.vhd(49) " "Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal \"SFS\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 49 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "SFG clock.vhd(49) " "Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal \"SFG\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 49 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CONTROL CONTROL:U1 " "Info: Elaborating entity \"CONTROL\" for hierarchy \"CONTROL:U1\"" {  } { { "clock.vhd" "U1" { Text "E:/EDA2006073071/clock/clock.vhd" 52 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "QM control.vhd(15) " "Warning (10492): VHDL Process Statement warning at control.vhd(15): signal \"QM\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 15 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "QS control.vhd(16) " "Warning (10492): VHDL Process Statement warning at control.vhd(16): signal \"QS\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 16 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ENH control.vhd(11) " "Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable \"ENH\", which holds its previous value in one or more paths through the process" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ENM control.vhd(11) " "Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable \"ENM\", which holds its previous value in one or more paths through the process" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CPH control.vhd(11) " "Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable \"CPH\", which holds its previous value in one or more paths through the process" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CPM control.vhd(11) " "Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable \"CPM\", which holds its previous value in one or more paths through the process" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}