prev_cmp_clock.map.qmsg

用VHDL实现的完整数字钟代码

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT12_24 CNT12_24:U2 " "Info: Elaborating entity \"CNT12_24\" for hierarchy \"CNT12_24:U2\"" {  } { { "clock.vhd" "U2" { Text "E:/EDA2006073071/clock/clock.vhd" 53 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT60 CNT60:U3 " "Info: Elaborating entity \"CNT60\" for hierarchy \"CNT60:U3\"" {  } { { "clock.vhd" "U3" { Text "E:/EDA2006073071/clock/clock.vhd" 54 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LED LED:U5 " "Info: Elaborating entity \"LED\" for hierarchy \"LED:U5\"" {  } { { "clock.vhd" "U5" { Text "E:/EDA2006073071/clock/clock.vhd" 56 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FM FM:U6 " "Info: Elaborating entity \"FM\" for hierarchy \"FM:U6\"" {  } { { "clock.vhd" "U6" { Text "E:/EDA2006073071/clock/clock.vhd" 57 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "QFM timer.vhd(15) " "Warning (10631): VHDL Process Statement warning at timer.vhd(15): inferring latch(es) for signal or variable \"QFM\", which holds its previous value in one or more paths through the process" {  } { { "timer.vhd" "" { Text "E:/EDA2006073071/clock/timer.vhd" 15 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "QFM timer.vhd(15) " "Info (10041): Inferred latch for \"QFM\" at timer.vhd(15)" {  } { { "timer.vhd" "" { Text "E:/EDA2006073071/clock/timer.vhd" 15 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_LATCH_DISABLED" "FM:U6\|QFM " "Warning: LATCH primitive \"FM:U6\|QFM\" is permanently disabled" {  } { { "timer.vhd" "" { Text "E:/EDA2006073071/clock/timer.vhd" 11 -1 0 } }  } 0 0 "LATCH primitive \"%1!s!\" is permanently disabled" 0 0 "" 0 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "CNT12_24:U2\|Add0 lpm_add_sub " "Info: Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"CNT12_24:U2\|Add0\"" {  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "Add0" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\"" {  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"CNT12_24:U2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 4 " "Info: Parameter \"LPM_WIDTH\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CNT12_24:U2\|lpm_add_sub:Add0\|addcore:adder CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CNT12_24:U2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CNT12_24:U2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "f:/altera/quartus/libraries/megafunctions/addcore.tdf" 123 6 0 } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CNT12_24:U2\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "CNT12_24:U2\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs CNT12_24:U2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"CNT12_24:U2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "f:/altera/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "FeM GND " "Warning (13410): Pin \"FeM\" is stuck at GND" {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "CLK2048 " "Warning (15610): No output dependent on input pin \"CLK2048\"" {  } { { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 5 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "86 " "Info: Implemented 86 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Peak virtual memory: 174 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 04 16:49:13 2008 " "Info: Processing ended: Thu Dec 04 16:49:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}