clock.hif

用VHDL实现的完整数字钟代码

Version 8.0 Build 215 05/29/2008 SJ Web Edition
18
1139
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
lpm_add_sub
# storage
db|clock.(6).cnf
db|clock.(6).cnf
# case_insensitive
# source_file
f:|altera|quartus|libraries|megafunctions|lpm_add_sub.tdf
7ed3ce32dc22ef23ef21070b6a0bdff
6
# user_parameter {
LPM_WIDTH
4
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_njh
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
datab3
-1
1
datab2
-1
1
datab1
-1
1
cin
-1
1
}
# include_file {
f:|altera|quartus|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
f:|altera|quartus|libraries|megafunctions|alt_stratix_add_sub.inc
c08f604aefba5b4f1f554e565113c6
f:|altera|quartus|libraries|megafunctions|look_add.inc
ab9f577d30c5ef3166fab6c1c32c4a
f:|altera|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
f:|altera|quartus|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
f:|altera|quartus|libraries|megafunctions|alt_mercury_add_sub.inc
ae39f15ed67cc9a095d29f68f6ad0f8
f:|altera|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
}
# macro_sequence

# end
# entity
addcore
# storage
db|clock.(7).cnf
db|clock.(7).cnf
# case_insensitive
# source_file
f:|altera|quartus|libraries|megafunctions|addcore.tdf
2cad15b672cb85c21754eff1590dc6c
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
4
PARAMETER_UNKNOWN
USR
REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
}
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cin
-1
3
}
# include_file {
f:|altera|quartus|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
f:|altera|quartus|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
f:|altera|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
}
# macro_sequence

# end
# entity
a_csnbuffer
# storage
db|clock.(8).cnf
db|clock.(8).cnf
# case_insensitive
# source_file
f:|altera|quartus|libraries|megafunctions|a_csnbuffer.tdf
0a953daa377c9212d3c374d37725bd
6
# user_parameter {
WIDTH
4
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout0
-1
3
sin0
-1
3
}
# macro_sequence

# end
# entity
a_csnbuffer
# storage
db|clock.(9).cnf
db|clock.(9).cnf
# case_insensitive
# source_file
f:|altera|quartus|libraries|megafunctions|a_csnbuffer.tdf
0a953daa377c9212d3c374d37725bd
6
# user_parameter {
WIDTH
4
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout3
-1
3
sout2
-1
3
sout1
-1
3
sout0
-1
3
sin3
-1
3
sin2
-1
3
sin1
-1
3
sin0
-1
3
cout3
-1
3
cout2
-1
3
cout1
-1
3
cout0
-1
3
cin3
-1
3
cin2
-1
3
cin1
-1
3
cin0
-1
3
}
# macro_sequence

# end
# entity
altshift
# storage
db|clock.(10).cnf
db|clock.(10).cnf
# case_insensitive
# source_file
f:|altera|quartus|libraries|megafunctions|altshift.tdf
104af1c91d9166cdeca72d5b588cebf
6
# user_parameter {
WIDTH
4
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
altshift
# storage
db|clock.(11).cnf
db|clock.(11).cnf
# case_insensitive
# source_file
f:|altera|quartus|libraries|megafunctions|altshift.tdf
104af1c91d9166cdeca72d5b588cebf
6
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result0
-1
3
data0
-1
3
}
# macro_sequence

# end
# entity
LED
# storage
db|clock.(12).cnf
db|clock.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
led.vhd
3b8c9a15946a78ee2e4922d9ea9b20
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(adin)
23 downto 0
PARAMETER_STRING
USR
 constraint(seg)
6 downto 0
PARAMETER_STRING
USR
 constraint(sel)
2 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
LED:U5
}
# lmf
f:|altera|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
CNT60
# storage
db|clock.(3).cnf
db|clock.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt60.vhd
b73443ff4c33169eea1741aff386b
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(cout1)
3 downto 0
PARAMETER_STRING
USR
 constraint(cout2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
CNT60:U3
CNT60:U4
}
# lmf
f:|altera|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
clock
# storage
db|clock.(0).cnf
db|clock.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clock.vhd
d0fa83214ef63865af4e320fa72f8b
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
|
}
# lmf
f:|altera|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
CONTROL
# storage
db|clock.(1).cnf
db|clock.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
control.vhd
84101ecd385d64f0196553adc0d1c115
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
CONTROL:U1
}
# lmf
f:|altera|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
CNT12_24
# storage
db|clock.(2).cnf
db|clock.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt12_24.vhd
2e85634e786a281e419a9311f5fc
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(cout1)
3 downto 0
PARAMETER_STRING
USR
 constraint(cout2)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
CNT12_24:U2
}
# lmf
f:|altera|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
FM
# storage
db|clock.(4).cnf
db|clock.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
timer.vhd
72f47d88f66680bcd784b91645fbda13
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
 constraint(fs10)
3 downto 0
PARAMETER_STRING
USR
 constraint(fs1)
3 downto 0
PARAMETER_STRING
USR
 constraint(fm10)
3 downto 0
PARAMETER_STRING
USR
 constraint(fm1)
3 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
FM:U6
}
# lmf
f:|altera|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# complete