prev_cmp_clock.tan.qmsg

用VHDL实现的完整数字钟代码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "22 " "Warning: Found 22 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI2\[2\] " "Info: Detected ripple clock \"CNT60:U3\|CQI2\[2\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI2\[3\] " "Info: Detected ripple clock \"CNT60:U3\|CQI2\[3\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI2\[0\] " "Info: Detected ripple clock \"CNT60:U3\|CQI2\[0\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI2\[1\] " "Info: Detected ripple clock \"CNT60:U3\|CQI2\[1\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI1\[0\] " "Info: Detected ripple clock \"CNT60:U4\|CQI1\[0\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI1\[3\] " "Info: Detected ripple clock \"CNT60:U4\|CQI1\[3\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI1\[2\] " "Info: Detected ripple clock \"CNT60:U4\|CQI1\[2\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI1\[1\] " "Info: Detected ripple clock \"CNT60:U4\|CQI1\[1\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI2\[2\] " "Info: Detected ripple clock \"CNT60:U4\|CQI2\[2\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI2\[3\] " "Info: Detected ripple clock \"CNT60:U4\|CQI2\[3\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI2\[0\] " "Info: Detected ripple clock \"CNT60:U4\|CQI2\[0\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U4\|CQI2\[1\] " "Info: Detected ripple clock \"CNT60:U4\|CQI2\[1\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|CQI2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "CNT60:U4\|Equal1~31 " "Info: Detected gated clock \"CNT60:U4\|Equal1~31\" as buffer" {  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|Equal1~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "CNT60:U4\|Equal0~33 " "Info: Detected gated clock \"CNT60:U4\|Equal0~33\" as buffer" {  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U4\|Equal0~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "CONTROL:U1\|CPM~27 " "Info: Detected gated clock \"CONTROL:U1\|CPM~27\" as buffer" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 6 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CONTROL:U1\|CPM~27" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI1\[3\] " "Info: Detected ripple clock \"CNT60:U3\|CQI1\[3\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI1\[2\] " "Info: Detected ripple clock \"CNT60:U3\|CQI1\[2\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI1\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI1\[0\] " "Info: Detected ripple clock \"CNT60:U3\|CQI1\[0\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CNT60:U3\|CQI1\[1\] " "Info: Detected ripple clock \"CNT60:U3\|CQI1\[1\]\" as buffer" {  } { { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|CQI1\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "CNT60:U3\|Equal0~33 " "Info: Detected gated clock \"CNT60:U3\|Equal0~33\" as buffer" {  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|Equal0~33" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "CNT60:U3\|Equal1~31 " "Info: Detected gated clock \"CNT60:U3\|Equal1~31\" as buffer" {  } { { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CNT60:U3\|Equal1~31" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "CONTROL:U1\|CPH~27 " "Info: Detected gated clock \"CONTROL:U1\|CPH~27\" as buffer" {  } { { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 6 -1 0 } } { "f:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CONTROL:U1\|CPH~27" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK1 register CNT12_24:U2\|CQI2\[1\] register CNT12_24:U2\|CQI1\[1\] 45.05 MHz 22.2 ns Internal " "Info: Clock \"CLK1\" has Internal fmax of 45.05 MHz between source register \"CNT12_24:U2\|CQI2\[1\]\" and destination register \"CNT12_24:U2\|CQI1\[1\]\" (period= 22.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.300 ns + Longest register register " "Info: + Longest register to register delay is 15.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT12_24:U2\|CQI2\[1\] 1 REG LC2_C16 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C16; Fanout = 6; REG Node = 'CNT12_24:U2\|CQI2\[1\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CNT12_24:U2|CQI2[1] } "NODE_NAME" } } { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 4.500 ns CNT12_24:U2\|Equal4~18 2 COMB LC2_C14 2 " "Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC2_C14; Fanout = 2; COMB Node = 'CNT12_24:U2\|Equal4~18'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { CNT12_24:U2|CQI2[1] CNT12_24:U2|Equal4~18 } "NODE_NAME" } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 9.000 ns CNT12_24:U2\|CQI1~1260 3 COMB LC4_C13 2 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 9.000 ns; Loc. = LC4_C13; Fanout = 2; COMB Node = 'CNT12_24:U2\|CQI1~1260'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { CNT12_24:U2|Equal4~18 CNT12_24:U2|CQI1~1260 } "NODE_NAME" } } { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 11.900 ns CNT12_24:U2\|CQI1~1261 4 COMB LC2_C13 1 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 11.900 ns; Loc. = LC2_C13; Fanout = 1; COMB Node = 'CNT12_24:U2\|CQI1~1261'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { CNT12_24:U2|CQI1~1260 CNT12_24:U2|CQI1~1261 } "NODE_NAME" } } { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 15.300 ns CNT12_24:U2\|CQI1\[1\] 5 REG LC5_C15 10 " "Info: 5: + IC(2.200 ns) + CELL(1.200 ns) = 15.300 ns; Loc. = LC5_C15; Fanout = 10; REG Node = 'CNT12_24:U2\|CQI1\[1\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { CNT12_24:U2|CQI1~1261 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns ( 52.94 % ) " "Info: Total cell delay = 8.100 ns ( 52.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns ( 47.06 % ) " "Info: Total interconnect delay = 7.200 ns ( 47.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.300 ns" { CNT12_24:U2|CQI2[1] CNT12_24:U2|Equal4~18 CNT12_24:U2|CQI1~1260 CNT12_24:U2|CQI1~1261 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "15.300 ns" { CNT12_24:U2|CQI2[1] {} CNT12_24:U2|Equal4~18 {} CNT12_24:U2|CQI1~1260 {} CNT12_24:U2|CQI1~1261 {} CNT12_24:U2|CQI1[1] {} } { 0.000ns 2.200ns 2.200ns 0.600ns 2.200ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.300 ns - Smallest " "Info: - Smallest clock skew is -3.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 27.200 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 27.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK1 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'CLK1'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns CNT60:U4\|CQI2\[0\] 2 REG LC4_A16 5 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC4_A16; Fanout = 5; REG Node = 'CNT60:U4\|CQI2\[0\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK1 CNT60:U4|CQI2[0] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 8.800 ns CNT60:U4\|Equal1~31 3 COMB LC5_A16 3 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 8.800 ns; Loc. = LC5_A16; Fanout = 3; COMB Node = 'CNT60:U4\|Equal1~31'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CNT60:U4|CQI2[0] CNT60:U4|Equal1~31 } "NODE_NAME" } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 11.200 ns CONTROL:U1\|CPM~27 4 COMB LC2_A16 8 " "Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 11.200 ns; Loc. = LC2_A16; Fanout = 8; COMB Node = 'CONTROL:U1\|CPM~27'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CNT60:U4|Equal1~31 CONTROL:U1|CPM~27 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.100 ns) 15.000 ns CNT60:U3\|CQI1\[0\] 5 REG LC6_A20 6 " "Info: 5: + IC(2.700 ns) + CELL(1.100 ns) = 15.000 ns; Loc. = LC6_A20; Fanout = 6; REG Node = 'CNT60:U3\|CQI1\[0\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { CONTROL:U1|CPM~27 CNT60:U3|CQI1[0] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 17.400 ns CNT60:U3\|Equal0~33 6 COMB LC1_A20 7 " "Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 17.400 ns; Loc. = LC1_A20; Fanout = 7; COMB Node = 'CNT60:U3\|Equal0~33'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CNT60:U3|CQI1[0] CNT60:U3|Equal0~33 } "NODE_NAME" } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.800 ns) 21.500 ns CONTROL:U1\|CPH~27 7 COMB LC1_A16 8 " "Info: 7: + IC(2.300 ns) + CELL(1.800 ns) = 21.500 ns; Loc. = LC1_A16; Fanout = 8; COMB Node = 'CONTROL:U1\|CPH~27'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { CNT60:U3|Equal0~33 CONTROL:U1|CPH~27 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 27.200 ns CNT12_24:U2\|CQI1\[1\] 8 REG LC5_C15 10 " "Info: 8: + IC(5.700 ns) + CELL(0.000 ns) = 27.200 ns; Loc. = LC5_C15; Fanout = 10; REG Node = 'CNT12_24:U2\|CQI1\[1\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { CONTROL:U1|CPH~27 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.200 ns ( 44.85 % ) " "Info: Total cell delay = 12.200 ns ( 44.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.000 ns ( 55.15 % ) " "Info: Total interconnect delay = 15.000 ns ( 55.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "27.200 ns" { CLK1 CNT60:U4|CQI2[0] CNT60:U4|Equal1~31 CONTROL:U1|CPM~27 CNT60:U3|CQI1[0] CNT60:U3|Equal0~33 CONTROL:U1|CPH~27 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "27.200 ns" { CLK1 {} CLK1~out {} CNT60:U4|CQI2[0] {} CNT60:U4|Equal1~31 {} CONTROL:U1|CPM~27 {} CNT60:U3|CQI1[0] {} CNT60:U3|Equal0~33 {} CONTROL:U1|CPH~27 {} CNT12_24:U2|CQI1[1] {} } { 0.000ns 0.000ns 2.500ns 0.600ns 0.600ns 2.700ns 0.600ns 2.300ns 5.700ns } { 0.000ns 2.800ns 1.100ns 1.800ns 1.800ns 1.100ns 1.800ns 1.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 30.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 30.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns CLK1 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'CLK1'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA2006073071/clock/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns CNT60:U4\|CQI1\[3\] 2 REG LC2_A18 3 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_A18; Fanout = 3; REG Node = 'CNT60:U4\|CQI1\[3\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { CLK1 CNT60:U4|CQI1[3] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.300 ns CNT60:U4\|Equal0~33 3 COMB LC1_A18 7 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 9.300 ns; Loc. = LC1_A18; Fanout = 7; COMB Node = 'CNT60:U4\|Equal0~33'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { CNT60:U4|CQI1[3] CNT60:U4|Equal0~33 } "NODE_NAME" } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.300 ns) 13.700 ns CONTROL:U1\|CPM~27 4 COMB LC2_A16 8 " "Info: 4: + IC(2.100 ns) + CELL(2.300 ns) = 13.700 ns; Loc. = LC2_A16; Fanout = 8; COMB Node = 'CONTROL:U1\|CPM~27'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { CNT60:U4|Equal0~33 CONTROL:U1|CPM~27 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.100 ns) 17.400 ns CNT60:U3\|CQI2\[2\] 5 REG LC3_A13 4 " "Info: 5: + IC(2.600 ns) + CELL(1.100 ns) = 17.400 ns; Loc. = LC3_A13; Fanout = 4; REG Node = 'CNT60:U3\|CQI2\[2\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { CONTROL:U1|CPM~27 CNT60:U3|CQI2[2] } "NODE_NAME" } } { "cnt60.vhd" "" { Text "E:/EDA2006073071/clock/cnt60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 20.300 ns CNT60:U3\|Equal1~31 6 COMB LC1_A13 3 " "Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 20.300 ns; Loc. = LC1_A13; Fanout = 3; COMB Node = 'CNT60:U3\|Equal1~31'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { CNT60:U3|CQI2[2] CNT60:U3|Equal1~31 } "NODE_NAME" } } { "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "f:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 24.800 ns CONTROL:U1\|CPH~27 7 COMB LC1_A16 8 " "Info: 7: + IC(2.200 ns) + CELL(2.300 ns) = 24.800 ns; Loc. = LC1_A16; Fanout = 8; COMB Node = 'CONTROL:U1\|CPH~27'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { CNT60:U3|Equal1~31 CONTROL:U1|CPH~27 } "NODE_NAME" } } { "control.vhd" "" { Text "E:/EDA2006073071/clock/control.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.700 ns) + CELL(0.000 ns) 30.500 ns CNT12_24:U2\|CQI2\[1\] 8 REG LC2_C16 6 " "Info: 8: + IC(5.700 ns) + CELL(0.000 ns) = 30.500 ns; Loc. = LC2_C16; Fanout = 6; REG Node = 'CNT12_24:U2\|CQI2\[1\]'" {  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { CONTROL:U1|CPH~27 CNT12_24:U2|CQI2[1] } "NODE_NAME" } } { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.200 ns ( 46.56 % ) " "Info: Total cell delay = 14.200 ns ( 46.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.300 ns ( 53.44 % ) " "Info: Total interconnect delay = 16.300 ns ( 53.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "30.500 ns" { CLK1 CNT60:U4|CQI1[3] CNT60:U4|Equal0~33 CONTROL:U1|CPM~27 CNT60:U3|CQI2[2] CNT60:U3|Equal1~31 CONTROL:U1|CPH~27 CNT12_24:U2|CQI2[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "30.500 ns" { CLK1 {} CLK1~out {} CNT60:U4|CQI1[3] {} CNT60:U4|Equal0~33 {} CONTROL:U1|CPM~27 {} CNT60:U3|CQI2[2] {} CNT60:U3|Equal1~31 {} CONTROL:U1|CPH~27 {} CNT12_24:U2|CQI2[1] {} } { 0.000ns 0.000ns 2.500ns 0.600ns 2.100ns 2.600ns 0.600ns 2.200ns 5.700ns } { 0.000ns 2.800ns 1.100ns 2.300ns 2.300ns 1.100ns 2.300ns 2.300ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "27.200 ns" { CLK1 CNT60:U4|CQI2[0] CNT60:U4|Equal1~31 CONTROL:U1|CPM~27 CNT60:U3|CQI1[0] CNT60:U3|Equal0~33 CONTROL:U1|CPH~27 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "27.200 ns" { CLK1 {} CLK1~out {} CNT60:U4|CQI2[0] {} CNT60:U4|Equal1~31 {} CONTROL:U1|CPM~27 {} CNT60:U3|CQI1[0] {} CNT60:U3|Equal0~33 {} CONTROL:U1|CPH~27 {} CNT12_24:U2|CQI1[1] {} } { 0.000ns 0.000ns 2.500ns 0.600ns 0.600ns 2.700ns 0.600ns 2.300ns 5.700ns } { 0.000ns 2.800ns 1.100ns 1.800ns 1.800ns 1.100ns 1.800ns 1.800ns 0.000ns } "" } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "30.500 ns" { CLK1 CNT60:U4|CQI1[3] CNT60:U4|Equal0~33 CONTROL:U1|CPM~27 CNT60:U3|CQI2[2] CNT60:U3|Equal1~31 CONTROL:U1|CPH~27 CNT12_24:U2|CQI2[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "30.500 ns" { CLK1 {} CLK1~out {} CNT60:U4|CQI1[3] {} CNT60:U4|Equal0~33 {} CONTROL:U1|CPM~27 {} CNT60:U3|CQI2[2] {} CNT60:U3|Equal1~31 {} CONTROL:U1|CPH~27 {} CNT12_24:U2|CQI2[1] {} } { 0.000ns 0.000ns 2.500ns 0.600ns 2.100ns 2.600ns 0.600ns 2.200ns 5.700ns } { 0.000ns 2.800ns 1.100ns 2.300ns 2.300ns 1.100ns 2.300ns 2.300ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "cnt12_24.vhd" "" { Text "E:/EDA2006073071/clock/cnt12_24.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.300 ns" { CNT12_24:U2|CQI2[1] CNT12_24:U2|Equal4~18 CNT12_24:U2|CQI1~1260 CNT12_24:U2|CQI1~1261 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "15.300 ns" { CNT12_24:U2|CQI2[1] {} CNT12_24:U2|Equal4~18 {} CNT12_24:U2|CQI1~1260 {} CNT12_24:U2|CQI1~1261 {} CNT12_24:U2|CQI1[1] {} } { 0.000ns 2.200ns 2.200ns 0.600ns 2.200ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.200ns } "" } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "27.200 ns" { CLK1 CNT60:U4|CQI2[0] CNT60:U4|Equal1~31 CONTROL:U1|CPM~27 CNT60:U3|CQI1[0] CNT60:U3|Equal0~33 CONTROL:U1|CPH~27 CNT12_24:U2|CQI1[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "27.200 ns" { CLK1 {} CLK1~out {} CNT60:U4|CQI2[0] {} CNT60:U4|Equal1~31 {} CONTROL:U1|CPM~27 {} CNT60:U3|CQI1[0] {} CNT60:U3|Equal0~33 {} CONTROL:U1|CPH~27 {} CNT12_24:U2|CQI1[1] {} } { 0.000ns 0.000ns 2.500ns 0.600ns 0.600ns 2.700ns 0.600ns 2.300ns 5.700ns } { 0.000ns 2.800ns 1.100ns 1.800ns 1.800ns 1.100ns 1.800ns 1.800ns 0.000ns } "" } } { "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "30.500 ns" { CLK1 CNT60:U4|CQI1[3] CNT60:U4|Equal0~33 CONTROL:U1|CPM~27 CNT60:U3|CQI2[2] CNT60:U3|Equal1~31 CONTROL:U1|CPH~27 CNT12_24:U2|CQI2[1] } "NODE_NAME" } } { "f:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/quartus/bin/Technology_Viewer.qrui" "30.500 ns" { CLK1 {} CLK1~out {} CNT60:U4|CQI1[3] {} CNT60:U4|Equal0~33 {} CONTROL:U1|CPM~27 {} CNT60:U3|CQI2[2] {} CNT60:U3|Equal1~31 {} CONTROL:U1|CPH~27 {} CNT12_24:U2|CQI2[1] {} } { 0.000ns 0.000ns 2.500ns 0.600ns 2.100ns 2.600ns 0.600ns 2.200ns 5.700ns } { 0.000ns 2.800ns 1.100ns 2.300ns 2.300ns 1.100ns 2.300ns 2.300ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}