led_run_test.tan.rpt

来自「走马灯设计」· RPT 代码 · 共 213 行 · 第 1/2 页

+-------+--------------+------------+-------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From  ; To          ; To Clock ;
+-------+--------------+------------+-------+-------------+----------+
; N/A   ; None         ; 0.492 ns   ; rst_n ; led[0]~reg0 ; mclk     ;
; N/A   ; None         ; 0.492 ns   ; rst_n ; led[1]~reg0 ; mclk     ;
; N/A   ; None         ; 0.492 ns   ; rst_n ; led[2]~reg0 ; mclk     ;
; N/A   ; None         ; 0.492 ns   ; rst_n ; led[3]~reg0 ; mclk     ;
+-------+--------------+------------+-------+-------------+----------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 6.890 ns   ; led[1]~reg0 ; led[1] ; mclk       ;
; N/A   ; None         ; 6.883 ns   ; led[0]~reg0 ; led[0] ; mclk       ;
; N/A   ; None         ; 6.447 ns   ; led[3]~reg0 ; led[3] ; mclk       ;
; N/A   ; None         ; 6.446 ns   ; led[2]~reg0 ; led[2] ; mclk       ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+-------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To          ; To Clock ;
+---------------+-------------+-----------+-------+-------------+----------+
; N/A           ; None        ; -0.440 ns ; rst_n ; led[0]~reg0 ; mclk     ;
; N/A           ; None        ; -0.440 ns ; rst_n ; led[1]~reg0 ; mclk     ;
; N/A           ; None        ; -0.440 ns ; rst_n ; led[2]~reg0 ; mclk     ;
; N/A           ; None        ; -0.440 ns ; rst_n ; led[3]~reg0 ; mclk     ;
+---------------+-------------+-----------+-------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Wed May 13 20:49:50 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led_run -c led_run_test --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "mclk" is an undefined clock
Info: Clock "mclk" Internal fmax is restricted to 275.03 MHz between source register "state[0]" and destination register "led[3]~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.077 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'state[0]'
            Info: 2: + IC(0.599 ns) + CELL(0.478 ns) = 1.077 ns; Loc. = LC_X1_Y17_N5; Fanout = 1; REG Node = 'led[3]~reg0'
            Info: Total cell delay = 0.478 ns ( 44.38 % )
            Info: Total interconnect delay = 0.599 ns ( 55.62 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "mclk" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N5; Fanout = 1; REG Node = 'led[3]~reg0'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "mclk" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'state[0]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "led[0]~reg0" (data pin = "rst_n", clock pin = "mclk") is 0.492 ns
    Info: + Longest pin to register delay is 3.409 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 6; PIN Node = 'rst_n'
        Info: 2: + IC(1.073 ns) + CELL(0.867 ns) = 3.409 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led[0]~reg0'
        Info: Total cell delay = 2.336 ns ( 68.52 % )
        Info: Total interconnect delay = 1.073 ns ( 31.48 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "mclk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "mclk" to destination pin "led[1]" through register "led[1]~reg0" is 6.890 ns
    Info: + Longest clock path from clock "mclk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'led[1]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.712 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'led[1]~reg0'
        Info: 2: + IC(1.588 ns) + CELL(2.124 ns) = 3.712 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'led[1]'
        Info: Total cell delay = 2.124 ns ( 57.22 % )
        Info: Total interconnect delay = 1.588 ns ( 42.78 % )
Info: th for register "led[0]~reg0" (data pin = "rst_n", clock pin = "mclk") is -0.440 ns
    Info: + Longest clock path from clock "mclk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 3.409 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 6; PIN Node = 'rst_n'
        Info: 2: + IC(1.073 ns) + CELL(0.867 ns) = 3.409 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led[0]~reg0'
        Info: Total cell delay = 2.336 ns ( 68.52 % )
        Info: Total interconnect delay = 1.073 ns ( 31.48 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed May 13 20:49:50 2009
    Info: Elapsed time: 00:00:01