led_run.v

来自「走马灯设计」· Verilog 代码 · 共 38 行

module led_run_test(mclk,rst_n,led);
input mclk,rst_n;
output [3:0] led;
reg [3:0] led;
reg [24:0] count;
reg [1:0] state;
wire clk;

always @ (posedge mclk or negedge rst_n)
if(!rst_n)
	begin	
		
count<=25'd0;
	end
else
	begin
		count=count+1'b1;
	end
assign clk=count[24];

always @ (posedge clk or negedge rst_n)
if(!rst_n)
	begin	
		state<=2'd0;
	end
else
	begin
		state=state+1'b1;
		case(state)
		2'b00:	led=4'b0001;
		2'b01:	led=4'b0010;
		2'b10:	led=4'b0100;
		2'b11:	led=4'b1000;
		endcase
	end
endmodule