led_run_test.map.qmsg

来自「走马灯设计」· QMSG 代码 · 共 10 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 13 20:49:42 2009 " "Info: Processing started: Wed May 13 20:49:42 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led_run -c led_run_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led_run -c led_run_test" {  } {  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "led_run.v(9) " "Warning: (10268) Verilog HDL information at led_run.v(9): Always Construct contains both blocking and non-blocking assignments" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 9 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "led_run.v(21) " "Warning: (10268) Verilog HDL information at led_run.v(21): Always Construct contains both blocking and non-blocking assignments" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 21 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led_run.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file led_run.v" { { "Info" "ISGN_ENTITY_NAME" "1 led_run_test " "Info: Found entity 1: led_run_test" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led_run_test " "Info: Elaborating entity \"led_run_test\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "12 " "Info: Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "6 " "Info: Implemented 6 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 13 20:49:42 2009 " "Info: Processing ended: Wed May 13 20:49:42 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}