led_run_test.tan.qmsg

走马灯设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 13 20:49:50 2009 " "Info: Processing started: Wed May 13 20:49:50 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off led_run -c led_run_test --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led_run -c led_run_test --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "mclk " "Info: Assuming node \"mclk\" is an undefined clock" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "mclk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mclk register register state\[0\] led\[3\]~reg0 275.03 MHz Internal " "Info: Clock \"mclk\" Internal fmax is restricted to 275.03 MHz between source register \"state\[0\]\" and destination register \"led\[3\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.077 ns + Longest register register " "Info: + Longest register to register delay is 1.077 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[0\] 1 REG LC_X1_Y17_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'state\[0\]'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { state[0] } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.599 ns) + CELL(0.478 ns) 1.077 ns led\[3\]~reg0 2 REG LC_X1_Y17_N5 1 " "Info: 2: + IC(0.599 ns) + CELL(0.478 ns) = 1.077 ns; Loc. = LC_X1_Y17_N5; Fanout = 1; REG Node = 'led\[3\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.077 ns" { state[0] led[3]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 44.38 % " "Info: Total cell delay = 0.478 ns ( 44.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.599 ns 55.62 % " "Info: Total interconnect delay = 0.599 ns ( 55.62 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.077 ns" { state[0] led[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.077 ns" { state[0] led[3]~reg0 } { 0.000ns 0.599ns } { 0.000ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { mclk } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns led\[3\]~reg0 2 REG LC_X1_Y17_N5 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N5; Fanout = 1; REG Node = 'led\[3\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.485 ns" { mclk led[3]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[3]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { mclk } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns state\[0\] 2 REG LC_X1_Y17_N9 6 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N9; Fanout = 6; REG Node = 'state\[0\]'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.485 ns" { mclk state[0] } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk state[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 state[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[3]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk state[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 state[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 6 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.077 ns" { state[0] led[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.077 ns" { state[0] led[3]~reg0 } { 0.000ns 0.599ns } { 0.000ns 0.478ns } } } { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[3]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk state[0] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 state[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { led[3]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { led[3]~reg0 } {  } {  } } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0}