miller.fit.summary

使用VHDL实现基带码中密勒码的编解码

Fitter Status : Successful - Thu May 14 00:25:38 2009
Quartus II Version : 8.0 Build 231 07/10/2008 SP 1 SJ Full Version
Revision Name : miller
Top-level Entity Name : miller_encoder
Family : Cyclone II
Device : EP2C5T144C6
Timing Models : Final
Total logic elements : 7 / 4,608 ( < 1 % )
    Total combinational functions : 7 / 4,608 ( < 1 % )
    Dedicated logic registers : 6 / 4,608 ( < 1 % )
Total registers : 6
Total pins : 5 / 89 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )