miller_encoder.vhd.bak

来自「使用VHDL实现基带码中密勒码的编解码」· BAK 代码 · 共 59 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity miller_encoder is
port(datain :in std_logic;
	 en   :in std_logic;
	 clk  :in std_logic;
	 encodeout:out std_logic_vector(1 downto 0)
	 );
end ;

architecture func of miller_encoder is
begin 
 process(en,clk,datain)
  variable sav1 :std_logic:='1';
  variable sav2 :std_logic_vector(1 downto 0):="01";
  begin
   if(en='0') then
    encodeout<="ZZ";
   else 
    if(clk 'event and clk='1')then
	 if(datain='1' and sav1='1' and sav2="01") then
	  encodeout<="10";
	  sav2:="10";
	  sav1:='1';
	 elsif(datain='1' and sav1='1' and sav2="10") then
	  encodeout<="01";
	  sav2:="01";
	  sav1:='1';
	 elsif(datain='0' and sav1='1' and sav2="01") then
	  encodeout<="11";
	  sav2:="11";
	  sav1:='0';
	 elsif(datain='0' and sav1='1' and sav2="10") then
	  encodeout<="00";
	  sav2:="00";
	  sav1:='0';
	 elsif(datain='0' and sav1='0' and sav2="00") then
	  encodeout<="11";
	  sav2:="11";
	  sav1:='0';
	 elsif(datain='0' and sav1='0' and sav2="11") then
	  encodeout<="00";
	  sav2:="11";
	  sav1:='0';
	 elsif(datain='1' and sav1='0' and sav2="00") then
	  encodeout<="01";
	  sav2:="01";
	  sav1:='1';
	 elsif(datain='1' and sav1='0' and sav2="11") then
	  encodeout<="10";
	  sav2:="10";
	  sav1:='1';
	 end if; 
    end if;
   end if;
  end process;
end func;